DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgement is made to a claim of priority to Taiwanese application TW112103675 filed on February 2nd, 2023. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Applicant's election without traverse of Group II (e.g. a method of manufacturing a chip package, read on by claims 3-4) and cancelation of claims 1-2, and 4 in the reply filed on May 14th,2026 are acknowledged.
The requirement is made FINAL, claim 3 is being examined on its merits at this time.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Wu (US20220139700A1) in view of Miccoli et al. (US20090121321A1) for the following reasons:
Regarding claim 3;
Wu teaches A method of manufacturing a chip package unit with an outer protective layer (e.g. Detailed description [0039]) comprising the steps of: Step S1: providing a wafer (e.g. Fig. 1 ref S11, Detailed description [0040] “S11: provide a substrate and divide it into a number of chip areas…”); wherein the wafer is provided with a plurality of rectangular dies arranged in an array and a plurality of cutting channels for dividing the wafer (e.g. Fig. 2 ref 112, 101; Detailed description [0043] – [0044] “… the substrate 10 provided in step S11 may include, but is not limited to, a silicon substrate. The substrate 10 is also formed with a scribe line 101, which divides the substrate 10 into a number of chip areas 102; the number of scribe lines 101 in the substrate and the number of chip areas 102 separated by the scribe lines 101 can be set according to actual needs. There is no limitation here… n an example, a chip may be formed in the chip area 102, (the chip is not shown, only the metal wires 112 in the chip are shown in FIGS. 2 and 3)…”); each of the cutting channels is disposed between the two adjacent rectangular dies (e.g. Fig. 2, see examiner markup); Step S2: forming at least one outer protective layer on a surface of the wafer (e.g. Fig. 1 ref S12, S13, Detailed description [0041]-[0042] “S12: form a protective layer on chip areas on the substrate;
S13: expose and develop the protective layer to form a plurality of grooves where the protective layer covers the chip areas, and the depth of the each of the grooves is less than the thickness of the protective layer.”); wherein the respective outer protective layers are covering the respective cutting channels of the wafer (e.g. Fig. 4-5 ref 12+16; Detailed description [0045]-[0047] “…after step S11, the following step further includes: forming a passivation layer 16 on the upper surface of the substrate 10, as shown in FIG. 4. The passivation layer 16 covers the chip area 102.); wherein in the step S2, a redistribution layer (RDL) is firstly formed on the surface of the wafer; the RDL includes at least one dielectric layer and at least one conductive circuit (e.g. Detailed description [0045]-[0047] “…The passivation layer 16 may include a single-layer structure or a stacked structure including multiple material layers… a spin coating process can be applied, but not limited to, to form the protective layer 12 on the upper surface of the passivation layer 16… e protective layer 12 may include any integrated circuit protective layer that can be removed by exposure and development, such as a photosensitive material layer…”); thereby the respective outer protective layers are further formed by the respective dielectric layers.
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Wu is silent to a step of performing a sawing process to divide the wafer into a plurality of chip package units as claimed.
However, in figures 5A-5E Miccoli et al. teaches a method of dicing a wafer by performing a sawing process in which a cutting tool is used to divide the rectangular dies from the wafer by cutting along the respective cutting channels of the wafer and thus a plurality of chip package units is formed (e.g. Detailed description [0057]-[0061]); wherein during the sawing process, the cutting tool is first cutting the respective outer protective layers on the wafer and then continuously moved downward to cut the respective cutting channels of the wafer; thereby four sides of the respective outer protective layers on the respective chip package units are flush with four sides of the rectangular die after being divided from the wafer and the respective outer protective layers on the respective chip package units are located on a surface of the rectangular die.
At the effective time of filing, it would have been obvious to someone having ordinary skill in the art to incorporate the method of dicing a wafer taught in Miccoli et al. into the method of manufacturing a chip package unit with an outer protective layer taught in Wu to complete the process sequence of forming individual chip package units because the intermediate product resulting from the method of Wu can reliably be singulated through a variety of methods (traditional sawing, laser etching, chemical etching, plasma etching, etc.) as well as is intended to be singulated due to the presence of scribe lines (e.g. Detailed description [0043]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Quan et al. (US5776798A) teaches a semiconductor package where each package site is covered by an encapsulant and method of making.
Farnworth et al. (US6908784B1) teaches a method of fabricating encapsulated semiconductor components.
Fukuyo et al. (US8263479B2) teaches a method of singulating semiconductor substrates.
Yoshikazu (US5989982A) teaches a semiconductor device (a chip package with resin on one side) and method of manufacturing the same.
Wang et al. (US9406625B2) teaches a protective film encapsulating structure for the semiconductor dice.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM ROBERT MANN whose telephone number is (571)270-0210. The examiner can normally be reached Monday thru Thursday 0800-1800 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM ROBERT MANN/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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