DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the first contact and circuit must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Page 20 lines 1-5 of the instant specification disclose a circuit in an insulating layer between substrate 20 and conductor 21. Fig. 7 illustrates substrate 20, conductor 21, but does not show the insulating layer, the circuit, or a first contact extending in a stacking direction through a plurality of first insulating layers and a plurality of second insulating layers. Subsequent figures, such as 11 and 14, show an unlabeled layer, presumed to be an insulating layer, between substrate 20 and conductor 21, as well as a plurality of unlabeled layers between conductive layers 23, presumed to be either first or second insulating layers. However, a contact extending through a plurality of alternating first insulating and second insulating layers, and the circuit, are not shown.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1 and 11 each recite “an interconnect connection area arranged between the first and second areas” in lines 2-4, “a plurality of first conductive layers alternately stacked with a plurality of first insulating layers” in lines 8-9, and “a first contact electrically connecting the upper interconnect and a circuit disposed under the first conductive layers in the interconnect connection area, the first contact extending in the stacking direction through the first insulating layers and a plurality of second insulating layers alternately stacked with the first insulating layers in the interconnect connection area” in lines 31-37.
The specification as originally filed includes support for a first stacked body of first insulators and first conductors in an active region, and a second stacked body of second insulators and second conductors in a non-active area (p. 58 line 24 – p. 59 line 24). P. 31 lines 22-26 and figs. 14-15 include support for a contact CCL in a dummy block DBLK electrically connected to an underlying circuit. However, this contact does not extend through alternating first and second insulating layers.
Accordingly, the application as originally filed does not provide support for the claimed feature of “the first contact extending in the stacking direction through the first insulating layers and a plurality of second insulating layers alternately stacked with the first insulating layers in the interconnect connection area” as recited in claims 1 and 11.
Claims 2-10 and 12-20 depend on claims 1 and 11, and are rejected under 35 USC § 112(a) for implicitly including the indefinite subject matter above.
For the purpose of compact prosecution, the Examiner has interpreted claims 1 and 11 to mean:
“…a first contact electrically connecting the upper interconnect and a circuit disposed under the first conductive layers in the interconnect connection area, the first contact extending in the stacking direction through a plurality of second conductive layers and a plurality of second insulating layers alternately stacked with the plurality of second conductive layers in the interconnect connection area…”
Allowable Subject Matter
Claims 1-20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to teach or clearly suggest the limitations stating:
“the first conductive layers are further disposed in first and second adjacent areas, the first adjacent area being disposed between the interconnect connection area and a first insulating structure of the insulating structures disposed on one side of a first block area facing to the interconnect connection area in the first direction, the first block area being closest to the interconnect connection area among the block areas in the first area, and the second adjacent area being disposed between the interconnect connection area and a second insulating structure of the insulating structures disposed on one side of a second block area facing to the interconnect connection area in the first direction, the second block area being closest to the interconnect connection area among the block areas in the second area, and
a distance between the first insulating structure and the second insulating structure in the first direction is larger than a distance between the first insulating structure and a third insulating structure of the insulating structures in the first direction, the third insulating structure being disposed on the other side of the first block area in the first direction” as recited in claims 1 and 11.
Matsuda et al. (PG Pub. No. US 2017/0098658 A1) teaches a memory device (figs. 11-13 among others) including a connection region (DR and/or CR) between active regions (MRa/MRb), the active regions comprising memory blocks (MB) with alternately stacked conductive layers and insulating layers (102/103), a plurality of insulating structures (SL), a plurality of memory pillars (105), an upper interconnect (110), and a circuit (¶ 0133). However, Matsuda does not teach the arrangement of adjacent area, block areas, and insulating structures as recited in claims 1 and 11.
Lee et al. (PG Pub. No. US 2020/0286829 A1) teaches a memory device (fig. 1A among others) including a connection region (CT) between active regions (MB1, MB2), the active regions comprising memory blocks with alternately stacked conductive layers and insulating layers (11A/12A, 11B/12B), a plurality of insulating structures (SLI1/SLI2), memory strings (¶ 0034) and a circuit (TR). However, Lee does not teach the arrangement of adjacent area, block areas, and insulating structures as recited in claims 1 and 11.
Claims 2-10 and 12-20 would be allowable for implicitly including the subject matter above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at 571-270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRIAN TURNER/Examiner, Art Unit 2818
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