Prosecution Insights
Last updated: October 02, 2026
Application No. 18/419,856

SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME

Non-Final OA §112
Filed
Jan 23, 2024
Priority
Apr 19, 2023 — RE 10-2023-0051464
Examiner
WARREN, MATTHEW E
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
892 granted / 1017 resolved
+19.7% vs TC avg
Moderate +5% lift
Without
With
+5.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
18 currently pending
Career history
1035
Total Applications
across all art units

Statute-Specific Performance

§101
1.0%
-39.0% vs TC avg
§103
52.3%
+12.3% vs TC avg
§102
35.1%
-4.9% vs TC avg
§112
9.5%
-30.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1017 resolved cases

Office Action

§112
DETAILED ACTION This Office Action is in response to the Election filed on May 18, 2026. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election with traverse of Species A, claims 1-3 and 7-12 in the reply filed on May 18, 2026 is acknowledged. The traversal is on the ground(s) that claims 4-6 depend from claim 1 and can be examined with claim 1 without serious burden. This is found persuasive and claims 4-6 will be included in the examination. Claims 13-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-12 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Claim 1 recites the limitation “the second interfacial surface is in a first interlayer insulating layer among interlayer insulating layers.” The specification and drawings do not show support for the limitation in question. It appears that any one of the interfacial surface layers are in upper layers other than the first interlayer insulating layers which are also alternately disposed with the gate electrodes. Furthermore the claims recite that the “second interfacial surface between the first contact portion and the second contact portion is on a second level higher than the first level.” This limitation appears to denote that the second interfacial surface is in an upper level which would not include what is considered a first layer. The limitation in question appears to not be supported by the specification and will be ignored until further clarification and/or amendment is provide. Allowable Subject Matter The claims have been rejected under 35 USC 112 First Paragraph. See the rejection above. However, there is no prior art rejection for the claims, as far as understood, since the prior art has not disclosed devices comprising a first interfacial surface between the first channel portion and the second channel portion is on a first level, and a second interfacial surface between the first contact portion and the second contact portion is on a second level higher than the first level. The closest prior art references of Toyama (US 9,806,093 B2), Choi (US Pub. 2024/0090228 A1), Jeong (US Pub. 2023/0189527 A1), Kim (US Pub. 2022/0139831 A1), Son (US Pub. 2021/0082841 A1), Yang (CN-115763427 A), and Kim (CN-115223997 A) do not disclose these features of the claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW E WARREN whose telephone number is (571)272-1737. The examiner can normally be reached Mon-Fri 10am - 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, KRETELIA GRAHAM can be reached at 571-272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MATTHEW E WARREN/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Jan 23, 2024
Application Filed
Aug 26, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12751025
INSULATING-GATE BIPOLAR TRANSISTORS INCLUDING A REVERSE CONDUCTING DIODE
3y 1m to grant Granted Sep 29, 2026
Patent 12745471
SOLID-STATE IMAGING DEVICE AND METHOD FOR PRODUCING SOLID-STATE IMAGING DEVICE
3y 2m to grant Granted Sep 22, 2026
Patent 12745654
SEMICONDUCTOR DEVICE AND POWER CONVERTER
2y 10m to grant Granted Sep 22, 2026
Patent 12745445
WIDE BAND GAP SEMICONDUCTOR DEVICE WITH SURFACE INSULATING FILM
2y 6m to grant Granted Sep 22, 2026
Patent 12740383
SEMICONDUCTOR DEVICE INCLUDING A METAL OXIDE INTERFACE LAYER AND METHODS FOR FORMING THE SAME
3y 2m to grant Granted Sep 15, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
93%
With Interview (+5.1%)
2y 7m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1017 resolved cases by this examiner. Grant probability derived from career allowance rate.

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