DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I and Species D (Fig. 6, claims 1-6, 8) in the reply filed on 7/20/2026 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 3, 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent No. 10,332,895 (Li) in view of U.S. Patent Application Publication No. 2013/0059424 (Lindsay) and U.S. Patent No. 7,632,745 (Chen).
Li discloses
1. A semiconductor device, comprising:
a substrate 101 including an NMOS region I and a PMOS region II;
a first gate electrode 105 in the NMOS region I; and
a second gate electrode 106, 107 in the PMOS region II,
wherein the first gate electrode 105 includes a first electrode pattern 115,
wherein the second gate electrode 106, 107 includes a second electrode pattern 115,
wherein the first gate electrode 105 further includes a first N-type conductive pattern 114 between the first electrode pattern 115 and the substrate 105,
wherein the second gate electrode 106, 107 further includes a P-type conductive pattern 113 between the second electrode pattern and the substrate 105, and
Li fails to disclose
the first and second gate electrodes are in the substrate; and
wherein the P-type conductive pattern includes molybdenum titanium nitride (MoTiN) or molybdenum silicon nitride (MoSiN).
Lindsay teaches
A semiconductor device comprising:
a p-channel transistor 216 and an n-channel transistor 218, both having recessed gate electrodes 126 in a substrate 102.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide first and second gate electrodes in the substrate in Li. The motivation would be to increase effective channel length and reduce short-channel effects while maintaining transistor density as taught by Lindsay ([0003]-[0008], [0025]-[0029]).
Chen teaches (column 5, lines 32-38; column 16, lines 1-63)
A semiconductor device comprising:
a gate electrode 500, wherein the P-type conductive pattern (PMOS transistor) includes molybdenum titanium nitride (MoTiN) or molybdenum silicon nitride (MoSiN).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a P-type conductive pattern including MoSiN in Li. The motivation would be to perform the known function of establishing the desired PMOS gate work function and such substitution would be based on its suitability for the intended purpose. See MPEP 2144.07.
Li discloses
3. The semiconductor device of claim 1, wherein the second gate electrode 106, 107 further includes a second N-type conductive pattern 114 between the P-type conductive pattern 113 and the second electrode pattern 115.
Li discloses
8. The semiconductor device of claim 1, wherein the first electrode pattern 33, 133 has a width, in a direction parallel to an upper surface of the substrate 101, larger than a width of the second electrode pattern 35, 115 in the direction.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Lindsay and Chen as applied to claim 1 above, and further in view of U.S. Patent No. 7,563,715 (Haukka).
The combination of references fails to teach
2. The semiconductor device of claim 1, wherein a content of titanium or silicon in the P-type conductive pattern is about 1.0 to 50.0 atomic percent (at.%).
Haukka teaches (column 8, line 46 to column 9, line 6; column 15, lines 21-34)
A semiconductor device comprising:
wherein a content of titanium or silicon (MoSiN) in the P-type conductive pattern is about 1.0 to 50.0 atomic percent (at.%) (3:1 Mo:Si precursor-cycle ratio).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a desired content of silicon in the P-type conductive pattern in the modified device of Li. The motivation would be to optimize the silicon content of the MoSiN P-type conductive pattern to obtain the desired PMOS work function, conductivity, and thermal stability as taught by Haukka (Summary).
Claim(s) 4, 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Lindsay and Chen as applied to claim 1 above, and further in view of U.S. Patent No. 8,895,400 (Seo).
The combination of references fails to teach
4. The semiconductor device of claim 1, wherein the substrate further includes a cell region, and wherein the semiconductor device further includes: a word line in the substrate in the cell region; and a cell gate insulating layer between the word line and the substrate.
Seo teaches (at least Fig. 11)
A semiconductor device comprising:
wherein the substrate 51 further includes a cell region 20, and
a word line 78’ in the substrate 51 in the cell region 20; and
a cell gate insulating layer 77 between the word line 78’ and the substrate 51.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a cell region, a word line and a cell gate insulating layer in the modified device of Li. The motivation would be these features are well-known in the art of semiconductors for high integration and improved electrical characteristics and reliability as shown in Seo. See MPEP 2144.03.
Seo teaches
5. The semiconductor device of claim 4, wherein a width of the word line 78’, in a direction parallel to an upper surface of the substrate 51, is smaller than a width of the first electrode pattern 87 or a width of the second electrode pattern 88 in the direction.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to make the cell word line narrower than the peripheral gate electrode fill portions in the modified device of Li. The motivation would be a predictable dimensional optimization for increased memory cell density. Seo teaches spacer-defined sub-resolution word-line trenches to increase cell array density, whereas peripheral circuit transistors need not be constrained to the cell array word line pitch. See MPEP 2144.05.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Lindsay, Chen, and Seo as applied to claim 4 above, and further in view of U.S. Patent No. 8,790,973 (Scheiper) and U.S. Patent Application Publication No. 2008/0211057 (Lee).
The combination of references fails to teach
6. The semiconductor device of claim 4, wherein the first N-type conductive pattern includes a first sub-N-type conductive pattern and a second sub-N-type conductive pattern, the first sub-N-type conductive pattern is between the substrate and the second sub-N-type conductive pattern, wherein the word line includes a first cell electrode pattern and a second cell electrode pattern sequentially stacked relative to one another, wherein the second sub-N-type conductive pattern and the first cell electrode pattern include titanium nitride, and wherein the second cell electrode pattern includes a material the same as materials of the first electrode pattern and the second electrode pattern.
Scheiper teaches
A semiconductor device comprising:
wherein the first N-type conductive pattern 401 includes a first sub-N-type conductive pattern 401a and a second sub-N-type conductive pattern 401b, the first sub-N-type conductive pattern 401a is between the substrate 101and the second sub-N-type conductive pattern 401b.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use a N-type stack in the modified device of Li. The motivation would be such an N-type stack provides work function setting with a topology suitable for gate etching and high manufacturability as taught by Scheiper (Background).
Lee teaches
A semiconductor device comprising:
wherein the word line 130, 140, 155 includes a first cell electrode pattern 130 and a second cell electrode pattern 140, 155 sequentially stacked relative to one another,
Scheiper teaches wherein the second sub-N-type conductive pattern 401b and Lee teaches the first cell electrode pattern 130 include titanium nitride, and
Lee teaches
wherein the second cell electrode pattern 140 includes a material the same as materials of the first electrode pattern and the second electrode pattern.
The use of a common low-resistance metal for cell and peripheral gate fill was known by Seo. Upper conductive layer 81 of tungsten or tungsten silicide are formed in common over peripheral gate conductive layers and word line structures. Peripheral gate lines 85, 87, 88 may likewise comprise tungsten or tungsten silicide.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to employ tungsten as the second electrode material in both the NMOS and PMOS gates and as the second cell electrode material in the modified device of Li. The motivation would be doings so uses a known low-resistance conductor in each structure and permits common materials / process integration. Seo expressly demonstrates common conductive material processing between cell word line structures and peripheral circuitry. Further, Lee teaches a buried word line structure for reducing the height of the semiconductor device and the degradation of oxide layers due to the application of a TiN metal gate ([0012]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Application Publication Nos. 2006/0027858 (Moon), 2006/0017104 (Yoon), 2007/0141773 (Kim) teach a PMOS gate stack designed for both manufacturability and thermal reliability.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
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/TERESA M. ARROYO/Primary Examiner, Art Unit 2893
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