DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-10,17-20 in the reply filed on 05/27/26 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10,17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi(USPGPUB DOCUMENT: 2019/0385997, hereinafter Choi) in view of Elsherbini(USPGPUB DOCUMENT: 2023/0163098, hereinafter Elsherbini).
Re claim 1 Choi discloses an integrated circuit (IC) package, comprising: a package substrate(102) including at least a first power node(left/right104) and a second power node(left/right104); an interposer(110) on the package substrate(102), the interposer(110) including: a insulating layer(110bd)[0048]; and a power management integrated circuit (PMIC(124)) embedded in the insulating layer(110bd)[0048], the PMIC(124) including a third power node(left/right126) and a fourth power node(left/right126), and the third power node(left/right126) being electrically coupled to the first power node(left/right104); and an IC die(120) on the interposer(110), the IC die(120) including a fifth power node(left/right122) and a sixth power node(left/right122), the fifth power node(left/right122) being electrically coupled to the fourth power node(left/right126), and the sixth power node(left/right122) being electrically coupled to the second power node(left/right104), wherein: the first power node(left/right104) and the third power node(left/right126) are configured to carry a first supply voltage[0130] having a first voltage level[0130], the fourth power node(left/right126) and the fifth power node(left/right122) are configured to carry a second supply voltage[0130] having a second voltage level[0130] different from the first voltage level[0130], the second power node(left/right104) and the sixth power node(left/right122) are configured to carry a third supply voltage[0130] having a third voltage level[0130] different from the first voltage level[0130] and the second voltage level[0130], and the PMIC(124) is configured to receive at the third power node(left/right126) the first supply voltage[0130], and output at the fourth power node(left/right126) the second supply voltage[0130].
Choi does not discloses the interposer(110) including: a dielectric layer(110bd)[0048]; the second power node(left/right104) and the sixth power node(left/right122) are configured to carry a third supply voltage having a ground voltage level or a third voltage level[0130] different from the first voltage level[0130] and the second voltage level[0130]
Elsherbini discloses the interposer including: a dielectric layer(114)[0080]; the second power node(left/right122) and the sixth power node(left/right122) are configured to carry a third supply voltage[0104] having a ground voltage level[0097] or a third voltage level[0104] different from the first voltage level and the second voltage level[0104]
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Elsherbini to the teachings of Choi in order to minimize challenges in power delivery network (PDN) design [0024, Elsherbini].
Re claim 2 Choi and Elsherbini disclose the IC package of claim 1, wherein: the PMIC(124) is further configured to output at the fourth power node(left/right126) the second supply voltage[0130] based on the PMIC(124) being at a power-on mode and to set the fourth power node(left/right126) at an open-circuit state based on the PMIC(124) being at a power-off mode.
Re claim 3 Choi and Elsherbini disclose the IC package of claim 1, wherein:the interposer(110) further comprises one or more conductive structures, the dielectric layer(110bd)[0048] surrounding the one or more conductive structures, andthe third power node(left/right126) is electrically coupled to the first power node(left/right104) through a first conductive structure of the one or more conductive structures.
Re claim 4 Choi and Elsherbini disclose the IC package of claim 1, wherein the interposer(110) further comprises: a first interposer(110) metallization structure on one side of the dielectric layer(110bd)[0048] facing the package substrate(102), a second interposer(110) metallization structure on another side of the dielectric layer(110bd)[0048] facing the IC die(120), or a combination thereof.
Re claim 5 Choi and Elsherbini disclose the IC package of claim 4, wherein: the first interposer(110) metallization structure comprises at least one conductive pattern under the PMIC(124).
Re claim 6 Choi and Elsherbini disclose the IC package of claim 1, wherein: the interposer(110) further comprises a capacitive device(106 of Elsherbini) including a seventh power node and an eighth power node, the seventh power node is electrically coupled to the fourth power node(left/right126) and the fifth power node(left/right122), and the eighth power node is electrically coupled to the second power node(left/right104) and the sixth power node(left/right122).
Re claim 7 Choi and Elsherbini disclose the IC package of claim 6, wherein the capacitive device(106 of Elsherbini) comprises: a deep trench capacitor structure, a metal-insulator-metal structure, a metal-oxide-metal structure, or a combination thereof.
Re claim 8 Choi and Elsherbini disclose the IC package of claim 1, wherein the IC die(120) comprises: based on the IC die(120) at a face-up position with respect to the package substrate(102), a Page 3 of 9 metallization portion facing the interposer(110), a device portion on the metallization portion, and a substrate portion on the device portion;or based on the IC die(120) at a face-down position with respect to the package substrate(102), the substrate portion facing the interposer(110) and including backside conductive structures formed therein, a device portion on the substrate portion, and a metallization portion on the device portion.
Re claim 9 Choi and Elsherbini disclose the IC package of claim 8, wherein: the third power node(left/right126) is electrically coupled to the first power node(left/right104) through a conductive pattern of the metallization portion of the IC die(120), a portion of the backside conductive structures, or a combination thereof.
Re claim 10 Choi and Elsherbini disclose the IC package of claim 1, wherein a thickness of the interposer(110) ranges from 30 micrometers (pm) to 60 pm.
Re claim 17 Choi discloses an electronic device, comprising: an integrated circuit (IC) package that comprises: a package substrate(102) including at least a first power node(left/right104) and a second power node(left/right104); an interposer(110) on the package substrate(102), the interposer(110) including: an insulating layer(110bd)[0048]; and a power management integrated circuit (PMIC(124)) embedded in the insulating layer(110bd)[0048], the PMIC(124) including a third power node(left/right126) and a fourth power node(left/right126), and the third power node(left/right126) being electrically coupled to the first power node(left/right104); and an IC die(120) on the interposer(110), the IC die(120) including, a fifth power node(left/right122) and a sixth power node(left/right122), the fifth power node(left/right122) being electrically coupled to the fourth power node(left/right126), and the sixth power node(left/right122) being electrically coupled to the second power node(left/right104), wherein: the first power node(left/right104) and the third power node(left/right126) are configured to carry a first supply voltage[0130] having a first voltage level[0130], the fourth power node(left/right126) and the fifth power node(left/right122) are configured to carry a second supply voltage[0130] having a second voltage level[0130] different from the first voltage level[0130], the second power node(left/right104) and the sixth power node(left/right122) are configured to carry a third voltage level[0130] different from the first voltage level[0130] and the second voltage level[0130], and the PMIC(124) is configured to receive at the third power node(left/right126) the first supply voltage[0130], and output at the fourth power node(left/right126) the second supply voltage[0130].
Choi does not discloses the interposer(110) including: a dielectric layer(110bd)[0048]; the second power node(left/right104) and the sixth power node(left/right122) are configured to carry a third supply voltage[0130] having a ground voltage level[0130] or a third voltage level[0130] different from the first voltage level[0130] and the second voltage level[0130],
Elsherbini discloses the interposer including: a dielectric layer(114)[0080]; the second power node(left/right122) and the sixth power node(left/right122) are configured to carry a third supply voltage[0104] having a ground voltage level[0097] or a third voltage level[0104] different from the first voltage level and the second voltage level[0104],
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Elsherbini to the teachings of Choi in order to minimize challenges in power delivery network (PDN) design [0024, Elsherbini].
Re claim 18 Choi and Elsherbini disclose the electronic device of claim 17, wherein: the PMIC(124) is further configured to output at the fourth power node(left/right126) the second supply voltage[0130] based on the PMIC(124) being at a power-on mode and to set the fourth power node(left/right126) at an open-circuit state during based on the PMIC(124) being at a power-off mode.
Re claim 19 Choi and Elsherbini disclose the electronic device of claim 17, wherein: the interposer(110) further comprises one or more conductive structures, the dielectric layer(110bd)[0048] surrounding the one or more conductive structures, and the third power node(left/right126) is electrically coupled to the first power node(left/right104) through a first conductive structure of the one or more conductive structures.
Re claim 20 Choi and Elsherbini disclose the electronic device of claim 17, wherein the interposer(110) further comprises: a first interposer(110) metallization structure on one side of the dielectric layer(110bd)[0048] facing the package substrate(102), a second interposer(110) metallization structure on another side of the dielectric layer(110bd)[0048] facing the IC die(120), or a combination thereof.
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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