Prosecution Insights
Last updated: October 02, 2026
Application No. 18/420,305

SEMICONDUCTOR DEVICE AND MOUNTING STRUCTURE FOR SEMICONDUCTOR DEVICE

Non-Final OA §103
Filed
Jan 23, 2024
Priority
Sep 06, 2021 — JP 2021-144534 +1 more
Examiner
BOOTH, RICHARD A
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Rohm Co., Ltd.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
921 granted / 1072 resolved
+17.9% vs TC avg
Moderate +8% lift
Without
With
+8.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
23 currently pending
Career history
1096
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
58.8%
+18.8% vs TC avg
§102
27.9%
-12.1% vs TC avg
§112
7.5%
-32.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1072 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1-9 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Meissner, DE 696 37 488 in view of JP 2008-124176. Meissner shows the invention substantially as claimed including a semiconductor device comprising: A semiconductor element (IGBT) 11; A sealing resin 2 having a first surface 21 facing in a thickness direction and covering the semiconductor element 11 (see fig. 3 and paragraphs 0083-0084 of translation); and A first signal terminal 5 electrically connected to the semiconductor element 11 (see fig. 3), wherein the sealing resin has a second surface on the same side as the first surface in the thickness direction (see fig. 3 and paragraphs 0079-0084 of translation); The first surface includes a first region 21 located opposite to the first signal terminal with the second surface interposed therebetween in a first direction orthogonal to the thickness direction (arranged between groove 21 and terminal 5), the first region being configured such that a mounting member is disposed thereon; and A position of the second surface differs from a position of the first region in the thickness direction (see figs. 1-3 and paragraphs 0074-0084). Messner does not expressly disclose that the first signal terminal protrudes from the first surface of the sealing resin. JP ‘176 discloses a first signal terminal 3 that protrudes from a first surface of the sealing resin 1 on the side opposing and parallel to a substrate surface 6 (see figs. 1, 3, and paragraphs 0007-0012). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Messner so as to have the first signal terminal protrude from the first surface because of the predictable results of providing connections to external devices would be attained. Regarding dependent claim 2, note that Messner discloses wherein the sealing resin includes a third surface (one vertical sidewall of recess 21—see fig. 3) facing in the first direction and located between the first region and the second surface in the thickness direction, and the third surface is located between the first region and the second surface in the first direction. Concerning dependent claim 3, note that Messner discloses wherein the second surface is located between the semiconductor element and the first region in the thickness direction, and the third surface faces toward the first signal terminal in the first direction (see fig. 3 of Messner). With respect to dependent claim 4, note that the sealing resin of Messner modified by JP 2008-124176 discloses a fourth surface (other vertical sidewall of recess 21---see fig. 3) located between the second surface and the first signal terminal in the first direction, and the fourth surface faces the third surface. As to dependent claim 5, note that in Messner the second surface and the third surface extend in a second direction orthogonal to the thickness direction and the first direction (see fig.3 of Messner). Concerning dependent claim 6, note that in Messner the second surface is located opposite to the semiconductor element 11 with the first region interposed therebetween in the thickness direction, and the third surfaces faces toward the first region in the first direction. Regarding dependent claim 7, note that Messner fails to expressly disclose the claimed second signal terminal. However, JP 2008-124176 discloses a second signal terminal protruding from the claimed first surface and electrically connected to the semiconductor element, wherein the second signal terminal is located next to the first signal terminal in a second direction orthogonal to the thickness and the first direction (see fig. 8 and its description). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the device of Messner so as to provide the claimed second signal terminal in order to allow for improved variety and communication between the different semiconductor elements. Furthermore, as to dependent claim 8, it would have been obvious to one of ordinary skill in the art at the time the invention was filed for the third surface to bridge between the first and second signal terminals as viewed in the first direction because in such a way improved connection between external devices can be realized. As to dependent claim 9, note that Messner discloses wherein the sealing resin includes a fourth surface located between the second surface and the first signal terminal in the first direction, and the fourth surface faces away from the third surface and is spaced apart from the first signal terminal. Regarding dependent claim 17, note that Messner discloses a mount structure of a semiconductor device, wherein the mounting member can be a conductor (see in paragraph 0084 the mention of a external radiation rib), and when the semiconductor device as set forth in claim 1 is mounted on a heat sink 51 using the mounting member, the mounting member is pressed against the first region (see fig. 3 of Messner). Claim(s) 12-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Meissner, DE 696 37 488 in view of JP 2008-124176 as applied to claims 1-9, and 17 above, and further in view of Usui, WO 2020/179369. Meissner and JP 2008-124176 is applied as above and Meissner additionally discloses the semiconductor element including a first element 11 and a second element 16 where the first and second element are electrically connected to each other. However, Meissner does not expressly disclose a first conductive layer and a second conductive layer spaced apart from each other in a first direction, where the first element is conductively bonded to a first conductive layer while the second element is conductively bonded to a second conductive layer. Usui discloses a semiconductor device comprising a first conductive layer 22a and a second conductive layer 22b spaced from each other in a first direction (see fig. 2 and its description). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the device of Meissner and JP ‘176 so as to comprise the claimed conductive layers and connecting the first and second elements thereto in order to enable electrical connection between these elements. Regarding dependent claims 13-15, Meissner and JP 2008-124176 are applied as above but do not expressly disclose where an input terminal is conductively bonded to the first conductive layer and the output terminal is conductively bonded to the second conductive layer. Usui discloses an input terminal 42 is conductively bonded to the first conductive layer 22a and the output terminal 43 is conductively bonded to the second conductive layer 22b a support member 29 located opposite to the semiconductor element with the first conductive layer 22a and the second conductive layer 22b interposed therebetween in the thickness direction, wherein the support member 20 includes an insulating layer 21, and the first and second conductive layers are bonded to the support member, where the thickness of the insulating layer 21 is smaller than a thickness of the first and second conductive layers 22a/22b (see figs. 2, 4 and paragraph 0037). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the device of Meissner modified by JP 2008-124176 so as to form the input/output terminal conductive layer configuration in order to obtain an electrically interconnected semiconductor device. Additionally, concerning dependent claim 16, note that the semiconductor device of Meissner modified by JP 2008-124176 discloses a heat dissipation layer 51 (see fig. 3 of Meissner) located opposite to the first and second conductive layer where a thickness of the heat dissipation layer is larger than a thickness of the insulating layer 21 in Usui. Allowable Subject Matter Claims 10-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: the prior art of record, particularly Messner does not expressly disclose, the following limitations in combination with the claimed limitations: wherein the sealing resin includes an inner circumferential surface standing on the first surface and surrounding the first signal terminal as viewed in the thickness direction, the inner circumferential surface includes the fourth surface, and a space between the inner circumferential surface and the first signal terminal is hollow, as required by dependent claim 10. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A BOOTH whose telephone number is (571)272-1668. The examiner can normally be reached Monday to Friday, 8:30 to 5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RICHARD A BOOTH/Primary Examiner, Art Unit 2812 August 19, 2026
Read full office action

Prosecution Timeline

Jan 23, 2024
Application Filed
Aug 21, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
94%
With Interview (+8.3%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1072 resolved cases by this examiner. Grant probability derived from career allowance rate.

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