DETAILED ACTION
The RCE filed January 20, 2026 has been entered. Claims 1-21 are pending. Claim 11 was cancelled. Claim 21 has been added. Claims 1, 12 and 18 are independent.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7-10, 12-14 and 18-21 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Jain (US 2021/0249059) in view of Hong (US 2018/0308533).
Regarding independent claim 1, Jain teaches a memory device comprising:
a cell array (see e.g., FIG. 1: 104 along with FIG. 2: 208) comprising a plurality of static random-access memory (SRAM) cells;
a row decoder (116) configured to drive a plurality of word lines of the plurality of SRAM cells based on a row address;
a data input/output circuit (114) connected to a plurality of bit lines of the cell array and connected to a sub-power line configured to supply cell voltage to the plurality of SRAM cells.
Jain’s word line pulse generator (see FIGS. 1-4) does not explicitly disclose a word line pulse generator configured to generate a word line pulse with a first pulse width that is adjusted according to a resistance of a selected word line among the plurality of word lines corresponding to the row address and to provide the word line pulse to the row decoder.
Hong teaches the deficiencies in e.g., FIGS. 2 and 5 and accompanying disclosure, e.g., para. 0030: … the length of a signal line affects the RC characteristics of that line (i.e., claimed resistance (and capacitance) of the word line) … As such, pulse widths of word lines signals can be made …; and para. 0036-0038, i.e., para. 0037: … thus it has different RC characteristics …
Further, as the RC delay of the near-end word line decreases and the RC delay of the far-end word line increases, the word line pulse width increases and decreases, respectively, is a well-known technology in memory devices.
For support, see for example, Dhani Reddy et al. (US 9,911,474), col. 3, lines 15-35, As mentioned above, … suffer from … RC delay, … reduces effective wordline pulse width, …
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Hong to the teaching of Jain such that a memory, as taught by Jain, utilizes a varied word line pulses adjusted RC delay, as taught by Hong, for the purpose of compensating the location of word lines, thereby achieving enhanced memory operations.
Regarding claim 2, Jain and Hong, as combined, teach the limitations of claim 1.
Jain further teaches the word line pulse generator comprises: a first pulse generation circuit configured to generate a first pulse signal based on a write enable signal or a read enable signal; a first inverter configured to invert the first pulse signal; a first row address tracking circuit configured to adjust a pull-down speed of the first inverter based on the row address; and a first logic gate unit configured to perform logical multiplication operation on an output of the first inverter and the first pulse signal to output the word line pulse (see FIGS. 3-7 and accompanying disclosure).
Regarding claim 3, Jain and Hong, as combined, teach the limitations of claim 2.
Jain further teaches the first row address tracking circuit comprises a plurality of first selection transistors, each of the plurality of first selection transistors having a drain which is connected to a pull-down transistor of the first inverter, a gate which is connected to a corresponding word line of the plurality of word lines, and a source which is connected to ground (see e.g., FIGS. 3-7 and accompanying disclosure).
Regarding claims 4 and 14, Jain and Hong, as combined, teach the limitations of claims 3 and 13, respectively.
Jain does not explicitly disclose a metal line connecting the drain of each of the plurality of first selection transistors to a source of the pull-down transistor; and a metal line connecting the drain of each of the plurality of second selection transistors to a source of the pull-down transistor of the second inverter.
However, metal line routing for a transistor in a memory device is a well-known technology for a type of memory (e.g., SRAM) for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize static random access memory used metal routing because these conventional technology are well established in the art of the memory devices.
Regarding claim 7, Jain and Hong, as combined, teach the limitations of claim 1.
Jain further teaches a write assist pulse generator configured to generate a write assist pulse with a second pulse width varying based on the row address (e.g., para. 0025: … the boost control circuit generates a control signal during low voltage write operation …, i.e., assisting write operation); and a write assist circuit configured to provide a write assist voltage (e.g., para. 0020: … a boost word input … vis VDDWL above the supply voltage level …) to a selected SRAM cell through a sub power line based on the write assist pulse during a write operation.
Regarding claim 8, Jain and Hong, as combined, teach the limitations of claim 7.
Jain further teaches the write assist pulse generator comprises: a second pulse generation circuit configured to generate a second pulse signal in response to the write enable signal; a second inverter configured to invert the second pulse signal; a second row address tracking circuit configured to adjust a pull-down speed of the second inverter based on the row address; and a second logic gate unit configured to perform logical product operation on an output of the second inverter and the second pulse signal to output the write assist pulse (see e.g., FIGS. 3-7 and accompanying disclosure).
Regarding claim 9, Jain and Hong, as combined, teach the limitations of claim 8.
Jain further teaches the write assist circuit is further configured to lower the cell voltage of the selected SRAM cell during a pulse duration of the write assist pulse (e.g., para. 0029: … boosted voltage above the supply voltage level is then applied to the word line based on the TRK_WL_DELAYED signal. The word line receives the boosted voltage for a period of time before that boosted voltage decays back to the supply voltage level (VDD)).
Regarding claim 10, Jain and Hong, as combined, teach the limitations of claim 9.
Jain further teaches the second row address tracking circuit comprises a plurality of second selection transistors, each of the plurality of second selection transistors having a drain which is connected to a pull-down transistor of the second inverter, a gate which is connected to a corresponding word line of the plurality of word lines, and a source which is connected to ground (see e.g., FIGS. 3-7 and accompanying disclosure).
Regarding independent claim 12, Jain teaches a pulse generator of a static random-access memory (SRAM) device, the pulse generator comprising:
a pulse generation circuit (see FIGS. 3-7) configured to generate a first pulse signal based on a write enable signal or a read enable signal (e.g., FIG. 3: WE);
a row address tracking circuit (see FIGS. 3-7) configured to generate a second pulse signal by delaying the first pulse signal based on a row address (e.g., FIG. 3: TRK_WL_DELAYED with PRE_DEC_O); and
a logic gate unit configured to generate a word line pulse or a write assist pulse of the SRAM device by performing logical multiplication operation of the first pulse signal and the second pulse signal (see FIG. 1 along with FIGS. 3-7, and accompanying disclosure).
Jain’s delaying the word line pulse does not explicitly pulse signal based on a selected word line among a plurality of word lines corresponding to a row address; and a pulse width of the word line pulse or the write assist pulse is adjusted according to a resistance of the selected word line among the plurality of word lines corresponding to the row address.
Hong teaches the deficiencies in e.g., FIGS. 2 and 5 and accompanying disclosure, e.g., para. 0030: … the length of a signal line affects the RC characteristics of that line (i.e., claimed resistance (and capacitance) of the word line) … As such, pulse widths of word lines signals can be made …; and para. 0036-0038, i.e., para. 0037: … thus it has different RC characteristics …
Further, as the RC delay of the near-end word line decreases and the RC delay of the far-end word line increases, the word line pulse width increases and decreases, respectively, is a well-known technology in memory devices.
For support, see for example, Dhani Reddy et al. (US 9,911,474), col. 3, lines 15-35, As mentioned above, … suffer from … RC delay, … reduces effective wordline pulse width, …
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Hong to the teaching of Jain such that a memory, as taught by Jain, utilizes a varied word line pulses adjusted RC delay, as taught by Hong, for the purpose of compensating the location of word lines, thereby achieving enhanced memory operations.
Regarding claim 13, Jain and Hong, as combined, teach the limitations of claim 12.
Jain further teaches the row address tracking circuit comprises: an inverter comprising a pull-up transistor and a pull-down transistor; and a plurality of selection transistors, each of the plurality of selection transistors having a drain which is connected to a source of the pull-down transistor, a gate which is connected to a corresponding word line of a plurality of word lines, and a source which is grounded (see e.g., FIGS. 3-7 and accompanying disclosure).
Regarding independent claim 18, Jain teaches a memory device comprising:
a cell array (see e.g., FIG. 1: 104 along with FIG. 2: 208) comprising a plurality of static random-access memory (SRAM) cells;
a row decoder (116) configured to drive a plurality of word lines of the plurality of SRAM cells based on a row address;
a data input/output circuit (114) connected to a plurality of bit lines of the cell array; a write assist circuit configured to supply a cell voltage or a write assist voltage to the plurality of SRAM cells through a sub power line;
a word line pulse generator (FIG. 1 along with FIG. 4) configured to generate a word line pulse with a first pulse width that varies based on the row address to provide the word line pulse to the row decoder (para. 0022: … an PREDEC_O signal indicates that the associated row of memory cells, i.e., varies based on the row address) and to provide the word line pulse to the row decoder (see FIGS. 1-7 and accompanying disclosure); and
a write assist pulse generator (e.g., para. 0025: … the boost control circuit generates a control signal during low voltage write operation …, i.e., assisting write operation) configured to generate a write assist pulse with a second pulse width that varies based on the row address (see FIGS. 1-7 and accompanying disclosure).
Jain’s pulse generator does not explicitly disclose a word line pulse generator configured to generate a word line pulse that is adjusted according to a resistance of a selected word line among the plurality of word lines corresponding to the row address and to provide the word line pulse to the row decoder.
Hong teaches the deficiencies in e.g., FIGS. 2 and 5 and accompanying disclosure, e.g., para. 0030: … the length of a signal line affects the RC characteristics of that line (i.e., claimed resistance (and capacitance) of the word line) … As such, pulse widths of word lines signals can be made …; and para. 0036-0038, i.e., para. 0037: … thus it has different RC characteristics …
Further, as the RC delay of the near-end word line decreases and the RC delay of the far-end word line increases, the word line pulse width increases and decreases, respectively, is a well-known technology in memory devices.
For support, see for example, Dhani Reddy et al. (US 9,911,474), col. 3, lines 15-35, As mentioned above, … suffer from … RC delay, … reduces effective wordline pulse width, …
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Hong to the teaching of Jain such that a memory, as taught by Jain, utilizes a varied word line pulses adjusted RC delay, as taught by Hong, for the purpose of compensating the location of word lines, thereby achieving enhanced memory operations.
Regarding claim 19, Jain and Hong, as combined, teach the limitations of claim 18.
Jain further teaches the word line pulse generator comprises: a first pulse generation circuit configured to generate a first pulse signal based on a write enable signal or a read enable signal; a first inverter configured to invert the first pulse signal; a first row address tracking circuit configured to adjust a pull-down speed of the first inverter according to the row address; and a first logic gate unit configured to perform logical multiplication operation on an output of the first inverter and the first pulse signal to generate the word line pulse (see e.g., FIGS. 3-7 and accompanying disclosure).
Regarding claim 20, Jain and Hong, as combined, teach the limitations of claim 18.
Jain further teaches the write assist pulse generator comprises: a second pulse generation circuit configured to generate a second pulse signal in response to the write enable signal; a second inverter configured to invert the second pulse signal; a second row address tracking circuit configured to adjust a pull-down speed of the second inverter based on the row address; and a second logic gate unit configured to perform logical product operation on an output of the second inverter and the second pulse signal to output the write assist pulse (see e.g., FIGS. 3-7 and accompanying disclosure).
Regarding claim 21, Jain and Hong, as combined, teach the limitations of claim 1.
Hong further teach a second pulse width of the word line pulse for a second bit cell is wider than the first pulse width of the word line pulse for a first bit cell according to a resistance of a word line corresponding to the second bit cell that is greater than a resistance of a word line corresponding to the first bit cell. (see FIGS. 2 and 5 and accompanying disclosure).
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of Hong for the same purpose of compensating the location of word lines, thereby achieving enhanced memory operations.
Claims 5-6 and 15-17 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Jain (US 2021/0249059) in view of in view of Hong (US 2018/0308533), further in view of Liang et al. (US 2018/0068714).
Regarding claims 5-6 and 15, Jain and Hong, as combined, teach the limitations of claims 2 and 12 respectively.
Jain does not explicitly disclose the word line pulse generator comprises a dummy line extending in a bit line direction at an output terminal of the first inverter; and the word line pulse generator comprises a column tracking circuit configured to delay the first pulse signal based on a number of columns of the cell array to transmit the first pulse signal with the delay to the first inverter.
However, dummy bit line in a column tracking system is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Liang et al. (US 2018/0068714), e.g., FIG. 2: Dummy BL, and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize static random access memory used dummy bit line in a tracking circuitry because these conventional technology are well established in the art of the memory devices.
Regarding claims 16-17, Jain and Hong, as combined, teach the limitations of claim 12.
Jain does not explicitly disclose the row address tracking circuit comprises a digital control delay line configured to be switched by the row address; and the digital control delay line comprises a switch or a tristate inverter configured to be turned on or off by the row address.
Liang et al. teach the deficiencies in e.g., FIGS. 6-7 and accompanying disclosure, i.e., tracking in/out with switches selected.
Jain and Liang are analogous art because they both are directed to SRAM tracking device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Jain with the specified features of Liang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Liang et al. to the teaching of Jain and Hong, as combined, such that a SRAM tracking, as taught by Jain and Hong, utilizes a switching structure, as taught by Liang et al., for the purpose of enabling dynamic tracking scheme structure (see Liang, para. 0081), thereby adapting tracking scheme depend on the row being access rather than depending on the worst case.
Response to Amendment
Applicant’s RCE filed January 20, 2026, with respect to the rejection(s) of claims 1-21 under 35 USC 102 and 103, have been fully considered but are moot in view of the new ground(s) of rejection.
Therefore, it is respectfully submitted that the examiner maintains the rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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/SUNG IL CHO/ Primary Examiner, Art Unit 2825
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