DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Claims 1, 2, 5-10, and 13-16 stand rejected under Section 103. Claims 1, 2, 5-10, and 13-16 stand rejected under Section 112(a) for lack of enablement and for failing to meet the written description requirement. The drawings stand objected.
Applicants amended claims independent claims 1 and 9, and canceled claims 2 and 10. Applicants argue that the application is in condition for allowance.
Turning first to the drawings: Applicants’ amendment is insufficient to overcome the drawing objection. In order for the projection of the second electrode on the substrate layer to be substantially located within a projection of the second active layer on the substrate, a plan view would be needed to show this claim limitation, or this limitation would have to be stated in the disclosure. Neither is present. For these reasons, the drawing objection is maintained. Further, a drawing objection directly to the newly added limitation is added for the same reason.
Next, the Section 112(a) enablement rejections: Applicants’ amendment address the previously noted Section 112(a) enablement rejections and are accepted and entered. No new matter has been added. The previously noted Section 112(a) enablement rejections are withdrawn.
Section 112(a) written description rejections: Applicants argue that the because the disclosure indicates that the first metal lines 109, the first electrode 107, and the second electrode 108 are disposed on a same layer, and the second metal line 119, the first source/drain 117, and the second source/drain 118 are disposed on a same layer provides support that the first metal lines 109, the first electrode 107, and the second electrode 108 are substantially flush with one another. Applicants rely on their Figure 9 for support for this limitation. However, Figure 9 is not indicated as being to scale. Furthermore, being on the same layer does not make the first metal lines 109, the first electrode 107, and the second electrode 108 substantially flush with one another. The underlying layer, second gate insulating layer 106, may have been deposited conformally, as is typical for gate insulating layers to ensure that their thicknesses are consistent. See, e.g., Kang, U.S. Pat. Pub. No. 2019/0288048, Figure 16 (shown below in the Section 103 rejections section) for examples of typical, conformally deposited, gate insulating layers (112, 113). Second gate insulating layer 106 is not disclosed as being polishing so as to have a flat surface, and nothing else in the description of second gate insulating layer indicates a flat surface. Compare “first and second planarization layers 120, 122,” which by their name, indicates a planar upper surface. Metallizations formed on planarization layers such as first and second planarization layers 120, 122 would be expected to be substantially flush. The same cannot be said for first metal lines 109, the first electrode 107, and the second electrode 108—support for this claim limitation is absent from the specification. For these reasons, the Office is maintaining the Section 112(a) written description rejections.
The Office adds further written description rejections directed to the newly added claim limitation in claims 1 and 9, as well as the requirement in both claims that a projection of the second electrode on the substrate layer be substantially located within a projection of the second active layer on the substrate layer. Because only a cross-section is provided, and no plan view, support for these claim limitations is absent from the specification.
Section 103 rejections: Applicants argue that the claims are allowable because Kang Figure 16 does not disclose that the first gate (G1) and the first electrode (C2) overlap, but are instead misaligned. The Office disagrees. Below is Kang Figure 16, which shows that projections of first electrode (C2) and first gate (G1) on the substrate layer (110) substantially align and substantially overlap as required by the claim:
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Applicants arguments as to Cho and Xie as noted, but moot.
The Section 103 rejections are updated for the changes to the claims, as noted below.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown:
“a projection of the second electrode [108] on the substrate layer [101] is substantially located within a projection of the second active layer [112] on the substrate layer [101]” of claim 1 and similar language in claim 9 must be shown or the feature(s) canceled from the claim(s). A cross-section is insufficient. No new matter should be entered.
“a projection of the first electrode [107] on the substrate layer [101] is substantially aligned with and substantially overlaps a projection of the first gate [105] on the substrate layer [101] along the direction perpendicular to the substrate layer [101]” of claim 1 and similar language in claim 9 must be shown or the feature(s) canceled from the claim(s). A cross-section is insufficient. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 5-9, and 13-16 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1: This claim is rejected on three bases. First, claim 1 requires the first metal lines 109 to be substantially flush with the first electrode 107 and the second electrode 108 along a direction parallel to the substrate layer 101. However, the disclosure makes no mention of this feature and the drawings are not noted as being to scale. Furthermore, gate insulating layer 106, which in the prior art is typically a conformal layer, see Kang Figure 16 for an example, is not noted as being polished, planarized, or otherwise made flush through a chemical-mechanical polishing (CMP) process. In addition, the surface of the gate insulating layer 106 would be expected to be elevated at the first transistor due to thickness difference due to the presence of first gate 105 and first active layer 103, which are not present under the first metal lines 109 or the second electrode 108. Because the originally filed disclosure does not support this limitation, claim 1 is rejected for failing to meet the written description requirement.
Second, claim 1 has been amended to require a projection of the second electrode 108 on the substrate layer 101 to be substantially located within a projection of the second active layer 112 on the substrate layer 101. However, the disclosure is silent as to this feature and no plan view drawing was provided with the originally filed disclosure that would otherwise support this claim limitation. The cross-section is insufficient because the boundaries of the second electrode 108 and the second active layer 112 outside the cross-section are not known. Because this claim limitation is not supported by the originally filed disclosure, claim 1 is rejected for failing to meet the written description requirement.
Lastly, claim 1 has been amended to require a projection of the first electrode 107 on the substrate layer 101 to be substantially aligned with and substantially overlap a projection of the first gate 105 on the substrate layer 101 along a direction perpendicular to the substrate layer 101. Again, the disclosure is silent as to this feature and no plan view drawing was provided with the originally filed disclosure that would otherwise support this claim limitation. The cross-section is insufficient because the boundaries of the first electrode 107 and the first gate 105 outside the cross-section are not known. Because this claim limitation is not supported by the originally filed disclosure, claim 1 is rejected for failing to meet the written description requirement.
Claims 5-8 are rejected for depending from rejected base claim 1.
Regarding claim 9: As with claim 1, claim 9 is rejected on three bases. First, claim 9 requires the first metal lines 109 to be substantially flush with the first electrode 107 and the second electrode 108 along a direction parallel to the substrate layer 101. The discussion from claim 1 is incorporated by reference. Because the originally filed disclosure does not support this limitation, claim 9 is rejected for failing to meet the written description requirement.
Second, claim 9 has been amended to require a projection of the second electrode 108 on the substrate layer 101 to be substantially located within a projection of the second active layer 112 on the substrate layer 101. However, the disclosure is silent as to this feature and no plan view drawing was provided with the originally filed disclosure that would otherwise support this claim limitation. The cross-section is insufficient because the boundaries of the second electrode 108 and the second active layer 112 outside the cross-section are not known. Because this claim limitation is not supported by the originally filed disclosure, claim 9 is rejected for failing to meet the written description requirement.
Lastly, claim 9 has been amended to require a projection of the first electrode 107 on the substrate layer 101 to be substantially aligned with and substantially overlap a projection of the first gate 105 on the substrate layer 101 along a direction perpendicular to the substrate layer 101. Again, the disclosure is silent as to this feature and no plan view drawing was provided with the originally filed disclosure that would otherwise support this claim limitation. The cross-section is insufficient because the boundaries of the first electrode 107 and the first gate 105 outside the cross-section are not known. Because this claim limitation is not supported by the originally filed disclosure, claim 9 is rejected for failing to meet the written description requirement.
Claims 13-16 are rejected for depending from rejected base claim 9.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-9, and 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kang, U.S. Pat. Pub. No. 2019/0288048, Figures 1 and 15-18, and further in view of Yang, U.S. Pat. Pub. No. 2020/0357829, Figure 8, Cho, U.S. Pat. Pub. No. 2021/0005693, Figure 9, and Xie, U.S. Pat. Pub. No. 2018/0217458, Figure 1.
Kang, Figures 1, 15:
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Kang, Figures 16, 17:
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Kang, Figure 18: Yang, Figure 8:
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Yang, Figure 7:
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Cho, Figure 9:
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Xie, Figure 1:
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Regarding claim 1: Kang Figures 1, 15, and 16 disclose an array substrate, comprising a bending area (BA) and a non-bending area (1A, 2A), wherein the array substrate further comprises: a substrate layer (110); an inorganic stacked layer (111, 112, 113, 115, 116) disposed on the substrate layer (110), wherein the inorganic stacked layer (111, 112, 113, 115, 116) is provided with a recess (OP) in the bending area (BA) and a plurality of first metal lines (213i, 213o) disposed in the non-bending (1A, 2A) area at two sides of the bending area (BA); a filling layer (160) filled in the recess (OP); and a second metal line (215) disposed on the inorganic stacked layer (111, 112, 113, 115, 116) and the filling layer (160); wherein a plurality of first thin-film transistors (TFTs) (T1) and a plurality of second TFTs (T2) are disposed on a part of the inorganic stacked layer (111, 112, 113, 115, 116) corresponding to the non-bending area (1A, 2A), the first TFTs (T1) are polycrystalline-silicon TFTs, and the second TFTs (T2) are oxide semiconductor (OS) TFTs; wherein each of the first TFTs (T1) comprises a first active layer (AS1), a first gate (G1), a first electrode (C2), and a first source/drain (SE1, DE1), which are stacked, each of the second TFTs (T2) comprises a second active layer (AO2), a second gate (G2), and a second source/drain (SE2, DE2), which are stacked, and the first source/drain (SE1, DE1) and the second source/drain (SE2, DE2) are disposed on a same layer; wherein the array substrate further comprises a first planarization layer (118) and a second planarization layer (119), which are stacked on the inorganic stacked layer (111, 112, 113, 115, 116), a third metal line (CM) is disposed on the first planarization layer (118), a pixel electrode (310) is disposed on the second planarization layer (119), and the pixel electrode (310) and the first source/drain (SE1, DE1) form a lap joint by the third metal line (CM), wherein the second gate (G2) and the second active layer (AO2) are arranged sequentially along a direction perpendicular to the substrate layer (110), are disposed insulatively from each other, and at least partially overlap each other along the direction perpendicular to the substrate layer (110); wherein a projection of the first electrode (C2) on the substrate layer (110) is substantially aligned with and substantially overlaps a projection of the first gate (G1) on the substrate layer (110) along the direction perpendicular to the substrate layer (110). Kang specification ¶¶ 133-155, 44, 45, 126-132, 35, 43, 47-50.
Kang is silent as to whether a drain of the first source/drain of the first TFTs is electrically connected to a second source of the second source/drain of the second TFTs, or whether the first TFTs (T1) are low-temperature polycrystalline-silicon (LTPS) TFTs. Kang does not disclose that each of the second TFTs (T2) comprises a second electrode in addition to the second active layer, the second gate, and the second source/drain, and thus does not disclose that the first electrode and the second electrode are disposed on a same layer. Kang is silent as to whether the pixel electrode (310) is an anode. Kang does not disclose wherein a projection of the third metal line (CM) on the substrate layer (101) at least partially overlaps a projection of the second active layer (AO2) on the substrate layer (101) to form an overlap region between the third metal line (CM) and the second active layer (AO2). Lastly, Kang is silent as to whether the third metal line, the second gate (G2), the second active layer (AO2), and the second electrode are arranged sequentially along a direction perpendicular to the substrate layer (110), are disposed insulatively from each other, and at least partially overlap each other along the direction perpendicular to the substrate layer (10), and the first metal lines (213i, 213o) are substantially flush with the first electrode (C2) and the second electrode along a direction parallel to the substrate layer (110), wherein a projection of the second electrode on the substrate layer (101) is substantially located within a projection of the second active layer (AO2) on the substrate layer (101).
Kang Figure 17, a slightly different embodiment from Kang Figure 16, discloses the first metal lines (213i, 213o) are on the same insulation layer (113) via gate insulator (115) as the first electrode (C2). See Kang Figure 17; Kang specification ¶¶ 156-164. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Kang Figures 1, 15, and 16 to include the Kang Figure 17 design because the modification would have involved the substitution of an equivalent known for the same purpose.
Kang Figure 18 discloses an equivalent circuit of a pixel of its display apparatus. Kang specification ¶ 165. In Kang Figure 18, a first drain of first source/drain of the first TFTs (T1) is electrically connected to the second source of the second source/drain of the second TFTs (T2). Id. ¶¶ 172, 173. (Note that the claim does not require direct physical connection.) One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Kang Figures 1, 15, and 16 to include the Kang Figure 18 equivalent circuit design because this design can be used to drive the pixel. Id.
To the extent that Kang does not disclose an array substrate, Yang Figure 8, directed to similar subject matter, discloses an array substrate. Yang Title, Abstract, specification ¶ 72. Furthermore, Yang discloses the use of low temperature polysilicon for a TFT. Id. ¶ 3. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Kang to use Kang in an array substrate and use LTPS for the active layer because the modification would have involved the substitution of an equivalent known for the same purpose.
Yang Figure 7 discloses an anode (800) in the position of the pixel electrode. Yang specification ¶ 70. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to use an anode for the pixel electrode because the modification would have involved the substitution of an equivalent known for the same purpose.
Cho Figure 9, directed to similar subject matter, discloses each of the second TFTs (330) comprises a second electrode (520), a second active layer (331a), a second gate (334), and a second source/drain (332, 333), and that the first electrode (510) of the first TFT (320) and the second electrode (520) are disposed on a same layer. Cho discloses a first planarization layer (117) and a second planarization layer (118), which are stacked on the inorganic stacked layer (111, 112, 113, 114, 115), a third metal line (160) is disposed on the first planarization layer (117), an anode (first electrode (170), which can be an anode) is disposed on the second planarization layer (118), and the anode (170) and the first source/drain (323) form a lap joint by the third metal line (160); wherein a projection of the third metal line (160) on the substrate layer (110) at least partially overlaps a projection of the second active layer (331a) on the substrate layer (110) to form an overlap region between the third metal line (160) and the second active layer (331a). Cho discloses that the third metal line (160), the second gate (334), the second active layer (331a), and the second electrode (520) are arranged sequentially along a direction perpendicular to the substrate layer (110), are disposed insulatively from each other, and at least partially overlap each other along the direction perpendicular to the substrate layer (110). Cho discloses that the first electrode (510) and second electrode (520) are on the same metallization layer. Lastly, Cho discloses that a projection of the second electrode (520) on the substrate layer (110) is substantially located within a projection of the second active layer (331) on the substrate layer (110). Cho specification ¶¶ 53-55, 73-75, 196, 208-211. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to include the Cho design because Cho’s second electrode (520) acts as a light shield, protecting second TFT, id. ¶ 211, and because the modification would have involved the substitution of an equivalent known for the same purpose. Once combined the combination discloses that the first metal lines are on the same insulation layer (via Kang gate insulator (115)/Cho first interlayer insulating layer (113)) as the first electrode and second electrode.
As a further point on the requirement that the projection of the second electrode on the substrate layer be substantially located within a projection of the second active layer on the substrate layer, the purpose of second electrode (520) is to block external light from reaching the channel region (331a) of the second active layer (331). Cho specification ¶ 211. Cho describes the second electrode (520) as having a width that can be formed larger than the width of the channel region (331a). Id. Thus, the second electrode (520) can be designed such that its projection on the substrate layer (110) can be completely located within the projection of the second active layer (331) because the channel region (331a) of the second active layer (331) is a central portion of the second active layer (331). Id.
For example, Xie Figure 1, directed to similar subject matter, discloses a light shield (3) made from metal, such that a projection of the second electrode/light shield (2) on the substrate layer (1) is completely located within a projection of the second active layer (5, 6, 7) on the substrate layer (1). See Xie Figure 1, Xie specification ¶¶ 25-28. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to include the Xie design because Xie’s second electrode (3) acts as a light shield, protecting second TFT. Id.
As for the remaining requirements that the first metal lines are flush with the first electrode and the second electrode along a direction parallel to the substrate, applicants’ disclosure does not indicate that these limitations are patentably significant. For these reasons, the differences are obvious variants over the prior art as patentably insignificant shape variations and a patentably insignificant rearrangement of parts.
To the extent that the requirement that the first metal lines are flush with the first electrode and the second electrode along a direction parallel to the substrate is a result of a process, the process limitation of how a layer is formed has no patentable weight in claims drawn to structure. Note that a product-by-process claim is directed to the product per se, not the process by which the product is made. In re Hirao, 190 USPQ 15 at 17 n. 3 (CCPA 1976). See also In re Brown, 173 USPQ 685, 688 (CCPA 1972); In re Luck, 177 USPQ 523, 525 (CCPA 1973); In re Fessman, 180 USPQ 324, 325-26 (CCPA 1974); In re Avery, 186 USPQ 161, 166-67 (CCPA 1975); In re Wertheim, 191 USPQ 90, 103 (CCPA 1976); and In re Marosi, 218 USPQ 289, 292-93 (Fed. Cir. 1983), all of which make it clear that it is the patentability of the final product per se which must be determined in a product-by-process claim, and not the patentability of the process, and that an old or obvious product by a new method is not patentable as a product, whether claimed in product-by-process claims or not. Note that the applicant has the burden of proof in such cases, according to case law.
Regarding claim 5, which depends from claim 1: The combination discloses the first metal lines (213i, 213o) and the second metal line (215) form a lap joint at the two sides of the bending area (BA). Kang specification ¶¶ 147-155.
Regarding claim 6, which depends from claim 5: The combination discloses the second metal line (215) crosses over the filling layer (160) and the recess (OP) and is connected respectively to the first metal lines (213i, 213o) on two opposite sides of the filling layer (160). Id.
Regarding claim 7, which depends from claim 1: The combination discloses the first metal lines (Kang, 213i, 213o) are on the same layer (113), via gate insulator Kang (115)/Cho (113), as the first electrode (Kang, C2; Cho, 510) and the second electrode (Cho, 520), and that the second metal line (215), the first source/drain (SE1, DE1), and the second source/drain (SE2, DE2) are disposed on a same layer. See Kang Figures 16, 17; Cho Figure 9. See Kang specification ¶¶ 160, 63.
Regarding claim 8, which depends from claim 1: The combination discloses the inorganic stacked layer comprises a buffer layer (Kang, 111; Cho, 111), a first gate insulating layer (Kang, 112; Cho, 112), a second gate insulating layer (Kang, 113; Cho, 113), a first dielectric layer (Cho, 114), a third gate insulating layer (Kang, 115; Cho, 115), and a second dielectric layer (Kang, 116; Cho, 116), which are stacked. Kang specification ¶¶ 57, 61, 63, 71, 74; Cho specification ¶ 42.
Regarding claim 9: Kang Figures 1, 15, and 16 disclose a display panel, comprising an array substrate, wherein the array substrate comprises a bending area (BA) and a non-bending area (1A, 2A), and further comprises: a substrate layer (110); an inorganic stacked layer (111, 112, 113, 115, 116) disposed on the substrate layer (110), wherein the inorganic stacked layer (111, 112, 113, 115, 116) is provided with a recess (OP) in the bending area (BA) and a plurality of first metal lines (213i, 213o) disposed in the non-bending (1A, 2A) area at two sides of the bending area (BA); a filling layer (160) filled in the recess (OP); and a second metal line (215) disposed on the inorganic stacked layer (111, 112, 113, 115, 116) and the filling layer (160); wherein a plurality of first thin-film transistors (TFTs) (T1) and a plurality of second TFTs (T2) are disposed on a part of the inorganic stacked layer (111, 112, 113, 115, 116) corresponding to the non-bending area (1A, 2A), the first TFTs (T1) are polycrystalline-silicon TFTs, and the second TFTs (T2) are oxide semiconductor (OS) TFTs; wherein each of the first TFTs (T1) comprises a first active layer (AS1), a first gate (G1), a first electrode (C2), and a first source/drain (SE1, DE1), which are stacked, each of the second TFTs (T2) comprises a second active layer (AO2), a second gate (G2), and a second source/drain (SE2, DE2), which are stacked, and the first source/drain (SE1, DE1) and the second source/drain (SE2, DE2) are disposed on a same layer; wherein the array substrate further comprises a first planarization layer (118) and a second planarization layer (119), which are stacked on the inorganic stacked layer (111, 112, 113, 115, 116), a third metal line (CM) is disposed on the first planarization layer (118), a pixel electrode (310) is disposed on the second planarization layer (119), and the pixel electrode (310) and the first source/drain (SE1, DE1) form a lap joint by the third metal line (CM), wherein the second gate (G2) and the second active layer (AO2) are arranged sequentially along a direction perpendicular to the substrate layer (110), are disposed insulatively from each other, and at least partially overlap each other along the direction perpendicular to the substrate layer (110); wherein a projection of the first electrode (C2) on the substrate layer (110) is substantially aligned with and substantially overlaps a projection of the first gate (G1) on the substrate layer (110) along the direction perpendicular to the substrate layer (110). Kang Title; Kang specification ¶¶ 133-155, 44, 45, 126-132, 35, 43, 47-50.
Kang is silent as to whether a drain of the first source/drain of the first TFTs is electrically connected to a second source of the second source/drain of the second TFTs, or whether the first TFTs (T1) are low-temperature polycrystalline-silicon (LTPS) TFTs. Kang does not disclose that each of the second TFTs (T2) comprises a second electrode in addition to the second active layer, the second gate, and the second source/drain, and thus does not disclose that the first electrode and the second electrode are disposed on a same layer. Kang is silent as to whether the pixel electrode (310) is an anode. Kang does not disclose wherein a projection of the third metal line (CM) on the substrate layer (101) at least partially overlaps a projection of the second active layer (AO2) on the substrate layer (101) to form an overlap region between the third metal line (CM) and the second active layer (AO2). Lastly, Kang is silent as to whether the third metal line, the second gate (G2), the second active layer (AO2), and the second electrode are arranged sequentially along a direction perpendicular to the substrate layer (110), are disposed insulatively from each other, and at least partially overlap each other along the direction perpendicular to the substrate layer (10), and the first metal lines (213i, 213o) are substantially flush with the first electrode (C2) and the second electrode along a direction parallel to the substrate layer (110), wherein a projection of the second electrode on the substrate layer (101) is substantially located within a projection of the second active layer (AO2) on the substrate layer (101).
Kang Figure 17, a slightly different embodiment from Kang Figure 16, discloses the first metal lines (213i, 213o) are on the same insulation layer (113) via gate insulator (115) as the first electrode (C2). See Kang Figure 17; Kang specification ¶¶ 156-164. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Kang Figures 1, 15, and 16 to include the Kang Figure 17 design because the modification would have involved the substitution of an equivalent known for the same purpose.
Kang Figure 18 discloses an equivalent circuit of a pixel of its display apparatus. Kang specification ¶ 165. In Kang Figure 18, a first drain of first source/drain of the first TFTs (T1) is electrically connected to the second source of the second source/drain of the second TFTs (T2). Id. ¶¶ 172, 173. (Note that the claim does not require direct physical connection.) One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Kang Figures 15 and 16 to include the Kang Figure 18 equivalent circuit design because this design can be used to drive the pixel. Id.
To the extent that Kang does not disclose an array substrate, Yang Figure 8, directed to similar subject matter, discloses an array substrate. Yang Title, Abstract, specification ¶ 72. Furthermore, Yang discloses the use of low temperature polysilicon for a TFT. Id. ¶ 3. Lastly, Yang discloses that its invention is directed to use in a display panel. See id. ¶ 58. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Kang to use Kang in an array substrate and display panel, and use LTPS for the active layer, because the modification would have involved the substitution of an equivalent known for the same purpose.
Yang Figure 7 discloses an anode (800) in the position of the pixel electrode. Yang specification ¶ 70. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to use an anode for the pixel electrode because the modification would have involved the substitution of an equivalent known for the same purpose.
Cho Figure 9, directed to similar subject matter, discloses each of the second TFTs (330) comprises a second electrode (520), a second active layer (331a), a second gate (334), and a second source/drain (332, 333), and that the first electrode (510) of the first TFT (320) and the second electrode (520) are disposed on a same layer. Cho discloses a first planarization layer (117) and a second planarization layer (118), which are stacked on the inorganic stacked layer (111, 112, 113, 114, 115), a third metal line (160) is disposed on the first planarization layer (117), an anode (first electrode (170), which can be an anode) is disposed on the second planarization layer (118), and the anode (170) and the first source/drain (323) form a lap joint by the third metal line (160); wherein a projection of the third metal line (160) on the substrate layer (110) at least partially overlaps a projection of the second active layer (331a) on the substrate layer (110) to form an overlap region between the third metal line (160) and the second active layer (331a). Cho discloses that the third metal line (160), the second gate (334), the second active layer (331a), and the second electrode (520) are arranged sequentially along a direction perpendicular to the substrate layer (110), are disposed insulatively from each other, and at least partially overlap each other along the direction perpendicular to the substrate layer (110). Cho discloses that the first electrode (510) and second electrode (520) are on the same metallization layer. Lastly, Cho discloses that a projection of the second electrode (520) on the substrate layer (110) is substantially located within a projection of the second active layer (331) on the substrate layer (110). Cho specification ¶¶ 53-55, 73-75, 196, 208-211. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to include the Cho design because Cho’s second electrode (520) acts as a light shield, protecting second TFT, id. ¶ 211, and because the modification would have involved the substitution of an equivalent known for the same purpose. Once combined the combination discloses that the first metal lines are on the same insulation layer (via Kang gate insulator (115)/Cho first interlayer insulating layer (113)) as the first electrode and second electrode.
As a further point on the requirement that the projection of the second electrode on the substrate layer be substantially located within a projection of the second active layer on the substrate layer, the purpose of second electrode (520) is to block external light from reaching the channel region (331a) of the second active layer (331). Cho specification ¶ 211. Cho describes the second electrode (520) as having a width that can be formed larger than the width of the channel region (331a). Id. Thus, the second electrode (520) can be designed such that its projection on the substrate layer (110) can be completely located within the projection of the second active layer (331) because the channel region (331a) of the second active layer (331) is a central portion of the second active layer (331). Id.
For example, Xie Figure 1, directed to similar subject matter, discloses a light shield (3) made from metal, such that a projection of the second electrode/light shield (2) on the substrate layer (1) is completely located within a projection of the second active layer (5, 6, 7) on the substrate layer (1). See Xie Figure 1, Xie specification ¶¶ 25-28. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to include the Xie design because Xie’s second electrode (3) acts as a light shield, protecting second TFT. Id.
As for the remaining requirements that the first metal lines are flush with the first electrode and the second electrode along a direction parallel to the substrate, applicants’ disclosure does not indicate that these limitations are patentably significant. For these reasons, the differences are obvious variants over the prior art as patentably insignificant shape variations and a patentably insignificant rearrangement of parts.
To the extent that the requirement that the first metal lines are flush with the first electrode and the second electrode along a direction parallel to the substrate is a result of a process, the process limitation of how a layer is formed has no patentable weight in claims drawn to structure. Note that a product-by-process claim is directed to the product per se, not the process by which the product is made. In re Hirao, 190 USPQ 15 at 17 n. 3 (CCPA 1976). See also In re Brown, 173 USPQ 685, 688 (CCPA 1972); In re Luck, 177 USPQ 523, 525 (CCPA 1973); In re Fessman, 180 USPQ 324, 325-26 (CCPA 1974); In re Avery, 186 USPQ 161, 166-67 (CCPA 1975); In re Wertheim, 191 USPQ 90, 103 (CCPA 1976); and In re Marosi, 218 USPQ 289, 292-93 (Fed. Cir. 1983), all of which make it clear that it is the patentability of the final product per se which must be determined in a product-by-process claim, and not the patentability of the process, and that an old or obvious product by a new method is not patentable as a product, whether claimed in product-by-process claims or not. Note that the applicant has the burden of proof in such cases, according to case law.
Regarding claim 13, which depends from claim 9: The combination discloses the first metal lines (213i, 213o) and the second metal line (215) form a lap joint at the two sides of the bending area (BA). Kang specification ¶¶ 147-155.
Regarding claim 14, which depends from claim 13: The combination discloses the second metal line (215) crosses over the filling layer (160) and the recess (OP) and is connected respectively to the first metal lines (213i, 213o) on two opposite sides of the filling layer (160). Id.
Regarding claim 15, which depends from claim 9: The combination discloses the first metal lines (Kang, 213i, 213o) are on the same layer (113), via gate insulator Kang (115)/Cho (113), as the first electrode (Kang, C2; Cho, 510) and the second electrode (Cho, 520), and that the second metal line (215), the first source/drain (SE1, DE1), and the second source/drain (SE2, DE2) are disposed on a same layer. See Kang Figures 16, 17; Cho Figure 9. See Kang specification ¶¶ 160, 63.
Regarding claim 16, which depends from claim 9: The combination discloses the inorganic stacked layer comprises a buffer layer (Kang, 111; Cho, 111), a first gate insulating layer (Kang, 112; Cho, 112), a second gate insulating layer (Kang, 113; Cho, 113), a first dielectric layer (Cho, 114), a third gate insulating layer (Kang, 115; Cho, 115), and a second dielectric layer (Kang, 116; Cho, 116), which are stacked. Kang specification ¶¶ 57, 61, 63, 71, 74; Cho specification ¶ 42.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Victoria K. Hall/Primary Examiner, Art Unit 2897