DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-2, 4-15, and 21-26 in the reply filed on 7/20/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-7, 10-13, 21-22, and 26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ware (US 2012/0254472).
With regard to claim 1, fig. 1 of Ware discloses a semiconductor device (“IC devices”, par [0028]), comprising: a semiconductor die (Memory 0, fig. 1) having a first non-volatile storage structure (closest leftmost “flash memory” in fig. 1, par [0029]) and a second non- volatile storage structure (closest rightmost “flash memory” in fig. 1, par [0029]); a first set of signal lines (closest leftmost “TSV 105” in fig. 1, par [0028]) communicatively coupling the first non-volatile storage structure (closest leftmost flash memory, fig. 1) to a controller die 101 of the semiconductor device (“IC devices”, par [0028]), the first set of signal lines provided in a first set of through silicon vias (TSVs) (“TSV”, par [0028]) and enabling a first set of data to be directly written to the first non-volatile storage structure (closest leftmost flash memory in fig. 1); and a second set of signal lines communicatively coupling the second non-volatile storage structure (closest rightmost flash memory in fig. 1) to the controller die 101 of the semiconductor device (“IC devices”, par [0028]), the second set of signal lines provided in a second set of TSVs (closest rightmost TSV 105, fig. 1) and enabling a second set of data to be directly written to the second non-volatile storage structure (closest rightmost 105, fig. 1) independently from, and in parallel (“parallel”, par [0029]) with, the first set of data.
With regard to claim 2, fig. 1 of Ware discloses that a TSV channel (TSV, fig. 1), the TSV channel (TSV, fig. 1) including at least one of a first signal line (closed leftmost TSV, fig. 1) from the first set of signal lines and a first signal line from the second set of signal lines (closed rightmost TSV, fig. 1).
With regard to claim 4, fig. 1 of Ware discloses at least a portion of the first set of TSVs (closest leftmost TSV, fig. 1) are positioned between the first non-volatile storage structure (portion of closest leftmost flash memory to left of closest leftmost TSV in fig. 1) and the second non-volatile storage structure (closest rightmost flash memory in fig. 1).
With regard to claim 5, fig. 1 of Ware discloses semiconductor die (“IC devices”, par [0028]) is a first semiconductor die (Memory 0, fig. 1), the semiconductor device (“IC devices”, par [0028]) further comprising: a second semiconductor die (Memory 1, fig. 1) stacked on the first semiconductor die (Memory 0, fig. 1) and having a third non-volatile storage structure (closest leftmost flash memory in Memory 1 in fig. 1) and a fourth non-volatile storage structure (closest rightmost flash memory in Memory 1 in fig. 1); a third set of signal lines (TSV) communicatively coupling the third non-volatile storage structure (closest leftmost flash memory in Memory 1 in fig. 1) to the controller die 101 of the semiconductor device (“IC devices”, par [0028]), the third set of signal lines (TSV) provided in a third set of TSVs (TSV) and enabling a third set of data to be directly written to the third non- volatile storage structure (closest leftmost flash memory in Memory 1 in fig. 1) independently from, and in parallel (“parallel”, par [0029]) with, the first set of data (data for closest leftmost flash memory in Memory 0 in fig. 1) and the second set of data (data for closest rightmost flash memory in Memory 0); and a fourth set of signal lines (TSV for closest rightmost flash memory in Memory 1) communicatively coupling the fourth non-volatile storage structure (closest rightmost flash memory in Memory 1) to the controller die 101 of the semiconductor device (“IC devices”, par [0028]), the fourth set of signal lines provided in a fourth set of TSVs (TSV) and enabling a fourth set of data to be directly written to the fourth non- volatile storage structure (closest rightmost flash memory in Memory 1) independently from and in parallel (“parallel”, par [0029]) with, the first set of data (data of closest leftmost flash), the second set of data (data of closest rightmost flash) and the third set of data (data of closest leftmost flash).
With regard to claim 6, fig. 1 of Ware discloses at least one TSV in the first set of TSVs and at least one TSV in the third set of TSVs communicatively couple the first non-volatile storage structure (closest leftmost flash in Memory 0) and the third non-volatile storage structure (closest leftmost flash in Memory 1).
With regard to claim 7, fig. 1 of Ware discloses at least one TSV from the third set of TSVs (closest leftmost TSV in Memory 1) and at least one TSV from the fourth set of TSVs (closest rightmost TSV in Memory 1) are positioned between the third non- volatile storage structure (portion of closest leftmost flash to the left to closest leftmost TSV in fig. 1) and the fourth non-volatile storage structure (portion of closest rightmost flash to the right of closest rightmost TSV in fig. 1).
With regard to claim 10, fig. 1 of Ware discloses a non-volatile memory device (“IC devices”, par [0028]), comprising: a first semiconductor die (memory 0) having a first non-volatile storage means (closest leftmost “flash memory” in fig. 1, par [0029]) and a second non- volatile storage means (closest rightmost “flash memory” in fig. 1, par [0029]), the first semiconductor die (Memory 0, fig. 1) being stacked on a control means 101 of the non- volatile memory device; a first group of via means (“TSV”, par [0028]) adjacent to the first non-volatile storage means (closest leftmost “flash memory” in fig. 1, par [0029]) and the second non-volatile storage means (closest rightmost “flash memory” in fig. 1, par [0029]), the first group of via means (tsv of Memory 0) being associated with signal means that directly couple the first non-volatile storage means (closest leftmost “flash memory” in fig. 1, par [0029]) to the control means 101 of the non-volatile storage memory device (“IC devices”, par [0028]) and independently directly couple the second non-volatile storage means (closest rightmost flash memory, fig. 1) to the control means 101 of the non-volatile memory device (“IC devices”, par [0028]); a second semiconductor die (Memory 1, fig. 1) stacked on the first semiconductor die (Memory 0, fig. 1), the second semiconductor die (Memory 1, fig. 1) having a third non-volatile storage means (closest leftmost flash memory in Memory 1, fig. 1) and a fourth non-volatile storage means (closest rightmost flash Memory 1, fig. 1); and a second group of via means (tsv to Memory 1, fig. 1) adjacent to the third non-volatile storage means (closest leftmost flash memory in Memory 1, fig. 1) and the fourth non-volatile storage means (closest rightmost flash Memory 1, fig. 1), the second group of via means being associated with signal means that directly couple the third non-volatile storage means (closest leftmost flash memory in Memory 1, fig. 1) to the control means 101 of the non- volatile memory device (“IC devices”, par [0028]) and independently directly couple the fourth non-volatile storage means (closest rightmost flash Memory 1, fig. 1) to the control means 101 of the non-volatile memory device (“IC devices”, par [0028]).
With regard to claim 11, fig. 1 of Ware discloses a plurality of via means provided on the first semiconductor die (Memory 0, fig. 1), the first plurality of via means being associated with signal means that directly couple one or more of the first non-volatile storage means (closest leftmost flash memory in Memory 0, fig. 1) and the second non-volatile storage means (closest rightmost flash memory in Memory 0, fig. 1) to the control means 101 of the non-volatile memory device (“IC devices”, par [0028]).
With regard to claim 12, fig. 1 of Ware discloses that the plurality of via means (TSV in middle of Memory 0, fig. 1) is provided in a middle portion of the first semiconductor die (Memory 0, fig. 1).
With regard to claim 13, fig. 1 of Ware discloses at least one via means in the first group of via means (left group of TSV in Memory 0) and at least one via means in the second group of via (left group of TSV in Memory 0) means communicatively couple the first non-volatile storage means (left flash memory in Memory 0) and the third non-volatile storage means (left flash memory in Memory 1).
With regard to claim 21, fig. 1 of Ware discloses at least one TSV of the first set of TSVs is positioned adjacent to the first non-volatile storage structure (left flash memory in Memory 0) and at least one TSV of the second set of TSVs is positioned adjacent to the second non-volatile storage structure (right flash memory in Memory 0).
With regard to claim 22, fig. 1 of Ware discloses at least a subset of the first set of TSVs (TSV of left flash memory in Memory 0) are positioned between the first non-volatile storage structure (portion of closest leftmost flash memory to the left of left TSV in Memory 0) and the second non-volatile storage structure (portion of closest rightmost flash memory to the right of right TSV).
With regard to claim 26, fig. 1 of Ware discloses a non-volatile memory device (“IC devices”, par [0028]), comprising: a controller die (Memory 0, fig. 1) having a plurality of through silicon vias (TSVs) 105; a plurality of vertically stacked semiconductor dies (Memory 0) coupled to the controller die 101, each semiconductor die (Memory 0, Memory 1) of the plurality of semiconductor dies 103 having a plurality of non-volatile storage structures (“flash memory”, par [0029]); and a plurality of signal lines, each signal line of the plurality of signal lines routed through respective TSVs 105 of the controller die 101 and the plurality of vertically stacked semiconductor dies 103, wherein each non-volatile storage structure of the plurality of non-volatile storage structures (“flash memory”, par [0029]) is directly and independently coupled to the controller die 101 via a dedicated set of signal lines, thereby enabling parallel access to each non-volatile storage structure (“flash memory”, par [0029]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-9 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Ware (US 2012/0254472) in view of Lee (US 2020/0192804).
With regard to claim 8, Ware does not disclose that the first non-volatile storage structure and the second non-volatile storage structure are three dimensional (3D) NAND planes.
However, fig. 17 of Lee discloses that the first non-volatile storage structure (left side of 1439_0) and the second non-volatile storage structure (right side of 1439_0) are three dimensional (3D) NAND planes (“NAND flash memory”, par [0218]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the flash memory of Ware with the NAND flash memory as taught in Lee in order to provide large inexpensive storage of data in the case where power is cut off. See par [0218] of Lee.
With regard to claim 9, Ware does not disclose a plurality of connection points provided on a bottom surface of the controller die, wherein each connection point of the plurality of connection points is associated with a TSV in the first set of TSVs and the second set of TSVs.
However, fig. 17 of Lee discloses a plurality of connection points (connection balls on top of 1431 in fig. 17) provided on a bottom surface of the controller die 310, wherein each connection point (connection balls on top of 1431 in fig. 17) of the plurality of connection points is associated with a TSV (“TSV”, par [0234]) in the first set of TSVs (left side of 1439_0) and the second set of TSVs (right side of 1439_0).
Therefore, it would have been obvious to one of ordinary skill in the art to form the memory controller of Ware with connections on the other side of the controller from the nonvolatile memory as taught in Lee in order to provide connection for more memory stacks. See par [0232] of Lee.
With regard to claim 14, Ware does not disclose that the first non-volatile storage means is a three-dimensional (3D) NAND plane.
However, fig. 17 of Lee discloses that the first non-volatile storage means (left side of 1439_0) is a three dimensional (3D) NAND planes (“NAND flash memory”, par [0218]).
Therefore, it would have been obvious to one of ordinary skill in the art to form the flash memory of Ware with the NAND flash memory as taught in Lee in order to provide large inexpensive storage of data in the case where power is cut off. See par [0218] of Lee.
With regard to claim 15, Ware does not disclose a plurality of connection means provided on a bottom surface of the control means, wherein each connection means of the plurality of connection means is associated with a TSV in the first group of via means and the second group of via means.
However, fig. 17 of Lee discloses a plurality of connection means (bump on 1431) provided on a bottom surface (top of 1431) of the control means 1431, wherein each connection means (bump on 1431) of the plurality of connection means is associated with a TSV (“TSV”, par [0234]) in the first group of via means (left TSV in 1439_0) and the second group of via means (right TSV in 1439_0).
Therefore, it would have been obvious to one of ordinary skill in the art to form the memory controller of Ware with connections on the other side of the controller from the nonvolatile memory as taught in Lee in order to provide connection for more memory stacks. See par [0232] of Lee.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Ware (US 2012/0254472) in view of Yang (US 2022/0384326).
With regard to claim 23, Ware does not disclose that each non-volatile storage structure of the semiconductor die is associated with a dedicated set of TSVs that is not shared with any other non-volatile storage structure.
However, fig. 11A of Yang discloses that each non-volatile storage structure of the semiconductor die is associated with a dedicated set (“multiple dedicated vertical bypasses 698”, par [0191]) of TSVs 157 that is not shared with any other non-volatile storage structure 251.
Therefore, it would have been obvious to one of ordinary skill in the art to form the TSVs of Ware with the dedicated vertical bypasses as taught in Yang in order to control data access to the memory chips. See par [0192] of Yang.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Ware (US 2012/0254472) in view of Fujiwara (US 2022/0293492).
Regarding claim 24, Ware does not disclose the first set of TSVs and the second set of TSVs are arranged in a grid pattern including rows and columns, and wherein at least one TSV in the grid is positioned adjacent to each of the first non-volatile storage structure and the second non-volatile storage structure.
However, fig. 1A of Fujiwara discloses the first set of TSVs (top left set of 100T) and the second set of TSVs (top right set of 100T) are arranged in a grid pattern including rows and columns, and wherein at least one TSV 100T in the grid is positioned adjacent to each of the first non-volatile (“non-violate memory”, par [0020]) storage structure (top left 100M) and the second non-volatile storage structure (top right 100M).
Therefore, it would have been obvious to one of ordinary skill in the art to form the TSV of Ware as the TSV grid as taught in Fujiwara in order to provide a power distribution structure of an IC package. See par [0021] of Fujiwara.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Ware (US 2012/0254472) in view of Ahn (US 2023/0290740).
With regard to claim 25, Ware does not disclose a TSV channel located in a central region of the semiconductor die, the TSV channel including a plurality of TSVs that extend through the semiconductor die and are aligned with corresponding TSVs of the controller die and at least one additional semiconductor die in a vertical stack.
However, fig. 1 of Ahn discloses a TSV channel (TSV in middle of 100(b)) located in a central region of the semiconductor die (bottom die of 10(b), the TSV channel (TSV in middle of 100(b)) including a plurality of TSVs (TSV in middle of 100(b)) that extend through the semiconductor die and are aligned with corresponding TSVs of the controller die 10(c) and at least one additional semiconductor die (top die of 10(b)) in a vertical stack 10(b).
Therefore, it would have been obvious to one of ordinary skill in the art to form the TSV of Ware in the central region as taught in Ahn in order to provide a way to connected the stacked multilayer structure. See par [0069] of Ahn.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN T LIU whose telephone number is (571)272-6009. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
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/BENJAMIN TZU-HUNG LIU/Primary Examiner, Art Unit 2893
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