Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A in the reply filed on 06/22/2022 is acknowledged.
Claims 10 and 17 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06/22/2022.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 16 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US20070082448A1, hereinafter Kim).
Regarding claim 16, Kim discloses a semiconductor device, comprising:
a bit line (See below annotated fig. 24B buried bit line 170);
an interlayer insulating layer on the bit line and having an opening (See below annotated fig. 24B substrate 100 covers buried bit line 170 and has trenches 116, as illustrated in fig. 12, within it);
a first gate electrode and a second gate electrode spaced apart from each other, in the opening (See below annotated fig. 24B first and second ring-shaped gates 122);
an active pattern between the first gate electrode and the second gate electrode, the active pattern being electrically connected to the bit line (See below annotated fig. 24B pillar 118 is disposed between the first and second ring-shaped gates 122);
a first etch stop layer on the first gate electrode (See below annotated fig. 24B first etch stop layer 142 disposed on first ring-shaped gate 122);
a second etch stop layer on the second gate electrode (See below annotated fig. 24B second etch stop layer 142 disposed on second ring-shaped gate 122);
a first dielectric layer at least between the first gate electrode and the active pattern (See below annotated fig. 24B first gate insulating layer 120 disposed between first ring-shaped gate 122 and pillar 118);
a second dielectric layer at least between the second gate electrode and the active pattern (See below annotated fig. 24B second gate insulating layer 120 disposed between second ring-shaped gate 122 and pillar 118);
a first contact plug in contact with the first etch stop layer and on the first etch stop layer (See below annotated fig. 24B first word line 190 in contact with and on first etch stop layer 142); and
a second contact plug in contact with the second etch stop layer and on the second etch stop layer (See below annotated fig. 24B second word line 190 in contact with and on second etch stop layer 142).
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Allowable Subject Matter
Claims 1-9 and 11-15 allowed.
Claim 18-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1 and its dependent claims. The closest prior art (US20190393222A1, US20070082448A1, US20180069117A1) teaches a semiconductor device, comprising:
an active pattern including a vertical active portion and a first bend portion, the vertical active portion extending in a vertical direction, and the first bend portion being bent from an upper region of the vertical active portion (Sharma fig. 1A channel 115 has a vertical portion and an upper bent portion that is bent from an upper region of channel 115);
a gate electrode spaced apart from the active pattern, at least a portion of the gate electrode facing the vertical active portion (Sharma fig. 1A gate electrode 112 spaced apart from and facing channel 115);
a dielectric layer at least between the active pattern and the gate electrode (Sharma fig. 1A gate dielectric 114); and
a contact plug (Kim, fig. 1A conductive layer 198).
However, the closest prior art does not teach in combination with the other claimed elements
an etch stop layer at least between an upper surface of the gate electrode and the first bend portion; and
a contact plug on the etch stop layer, the contact plug penetrating at least through the first bend portion.
Additionally, the closest prior art does not teach the above in combination with the further limitations of dependent claims.
Examiner notes that while there are embodiments within the prior art, see Kim fig. 1A, that teach an etch stop layer 142 disposed below word line 190, the cited prior art does not show an embodiment nor any motivation to combine embodiments such that an etch stop layer is disposed at least between an upper surface of the gate electrode and the first bend portion and the contact plug penetrates at least through the first bend portion of the active pattern in addition with the other limitations of the independent claim.
Regarding claim 12 and its dependent claims. The closest prior art (US20190393222A1, US20070082448A1, US20180069117A1) teaches a semiconductor device, comprising,
a bit line (See above annotated Kim fig. 24B buried bit line 170);
an active pattern electrically connected to the bit line (See below annotated fig. 24B pillar 118 is electrically connected to buried bit line 170);
a word line at a same level as at least a first portion of the active pattern (See above annotated Kim fig. 24B first word line 190 at same level as at least a first portion of pillar 118);
a dielectric layer at least between the active pattern and the word line (See above annotated Kim fig. 24B first gate insulating layer 120);
an etch stop layer having a portion at a same level as a second portion of the active pattern (See above annotated Kim fig. 24B etch stop layer 142 has a first portion at the same level as a portion of pillar 118), and an upper end of the active pattern being at a higher level than a lower surface of the etch stop layer (See above annotated Kim fig. 24B upper end of pillar 118 is at a higher level than etch stop layer 142).
However, the closest prior art does not teach in combination with the other claimed elements
a contact plug in contact with the etch stop layer on the etch stop layer and electrically connected to the active pattern, a lower surface of the contact plug being at a higher level than the lower surface of the etch stop layer.
Additionally, the closest prior art does not teach the above in combination with the further limitations of dependent claims.
Examiner notes that while there are embodiments within the prior art, see Kim fig. 1A, that teach an etch stop layer 142 disposed below word line 190, the cited prior art does not show an embodiment nor any motivation to combine embodiments such that a contact plug is in contact with the etch stop layer and on the etch stop layer and electrically connected to the active pattern with a lower surface of the contact plug being at a higher level than the lower surface of the etch stop layer in addition with the other limitations of the independent claim.
Regarding claim 18, the closest prior art (US20190393222A1, US20070082448A1, US20180069117A1) teaches the semiconductor device as claimed in claim 16, wherein the active pattern includes:
a first vertical active portion (See above annotated Kim fig. 24B leftmost pillar 118 is a first vertical portion);
a first upper bend portion that is bent from an upper region of the first vertical active portion in a first direction (See above annotated Kim fig. 24B leftmost pillar 118 has an upper portion that bends to the left);
a second vertical active portion (See above annotated Kim fig. 24B second pillar 118 from the left is a second vertical portion); and
a second upper bend portion that is bent from an upper region of the second vertical active portion in a second direction opposite to the first direction (See above annotated Kim fig. 24B second pillar from the left 118 has an upper portion that bends to the right), wherein:
the first vertical active portion faces the first gate electrode and the first etch stop layer (See above annotated Kim fig. 24B leftmost pillar 118 faces gate electrodes 122).
However, the closest prior art does not teach in combination with the other claimed elements
the first upper bend portion vertically overlaps the first gate electrode and the first etch stop layer, and
the second upper bend portion vertically overlaps the second gate electrode and the second etch stop layer.
Additionally, the closest prior art does not teach the above in combination with the further limitations of dependent claims.
Regarding claim 20, the closest prior art (US20190393222A1, US20070082448A1, US20180069117A1) teaches the semiconductor device as claimed in claim 16.
However, the closest prior art does not teach in combination with the other claimed elements
the first gate electrode includes a first vertical gate portion and a first horizontal gate portion extending from a lower region of the first vertical gate portion,
the second gate electrode includes a second vertical gate portion and a second horizontal gate portion extending from a lower region of the second vertical gate portion, and
the active pattern includes a region vertically overlapping the first horizontal gate portion and a region vertically overlapping the second horizontal gate portion.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLE LEON LINDSEY whose telephone number is (571)272-4028. The examiner can normally be reached Monday - Friday, 8:00 a.m. - 5:00 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COLE LEON LINDSEY/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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