DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I (claims 1-17) without traverse in the reply filed on 04/10/2026 is acknowledged. Claims 18-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Adusumilli et al.(US 11195715 B2)
Regarding claim 1, Adusumilli teaches,
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A structure (Fig. 18 as annotated above) comprising:
a first semiconductor layer (40, Col. 7 , l. 10) including a first section (section of 40 on right as marked) and a second section (section of 40 on left as marked) adjacent to the first section;
a second semiconductor layer (20, Col. 2, l. 63) including a first section (section of 20 on left as marked) and a semiconductor region (section of 20 directly above 40 as marked) that projects from the second section of the first semiconductor layer to the first section of the second semiconductor layer, and
the first section and the semiconductor region of the second semiconductor layer comprising one or more single-crystal semiconductor materials (col. 20, l. 67, col. 21, ll. 1-2: and
a first dielectric layer(layer of shallow trench isolation region 38 defining a dialectic layer , Col. 7, ll. 27-28) disposed between the first section of the first semiconductor layer and the first section of the second semiconductor layer(as seen).
Regarding claim 2, Adusumilli teaches the structure of claim 1 and further teaches , further comprising:a shallow trench isolation region (region of shallow trench isolation region 38) disposed between the first section of the first semiconductor layer and the second section of the first semiconductor layer(as seen).
Regarding claim 3, Adusumilli teaches the structure of claim 2 and further teaches , wherein the first dielectric layer is disposed over (interpreting “over” as “in a position that is covering something” see OVER | definition in the Cambridge English Dictionary) the first section of the first semiconductor layer and beneath the first section of the second semiconductor layer (as seen), and the first dielectric layer (layer of 38) extends across the shallow trench isolation region (region of 38).
Regarding claim 4, Adusumilli teaches the structure of claim 3 and further teaches , wherein the first dielectric layer extends over (interpreting “over” as “in a position that is covering something” see OVER | definition in the Cambridge English Dictionary) a portion of the second section of the first semiconductor layer (the first dielectric layer 38 extends over the second section of first semiconductor layer 40 viewing from left or right side of Fig. 18).
Regarding claim 8, Adusumilli teaches the structure of claim 1 and further teaches , wherein the semiconductor region of the second semiconductor layer (as marked) projects from the second section of the first semiconductor layer (as marked) above the first dielectric layer (as marked).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically teaches d as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Adusumilli et al. and further in view of Cheng et al. (US 9287264 B1).
Regarding claim 17, Adusumilli teaches the structure of claim 1 and further teaches , wherein the first section of the second semiconductor layer (section of 20 as marked) extends laterally over the first dielectric layer (38)
But Adusumilli does not explicitly teaches,
… by a distance of greater than or equal to 200 nanometers.
But Adusumilli additionally teaches,
The semiconductor layer 20 may have a varying thickness ( col. 3 l. 11-12) and the semiconductor layer 20 may include divots at the locations of the merged lateral growth fronts between the trenches 16 and over the dielectric layer 14(Figs. 2-3, Col. 3 ll. 10-14).
And Cheng teaches ,
a thin Si layer 104 may have a thickness of approximately 20 nm to 100 nm (Col. 3, ll. 12-13, Fig. 1).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to vary the thickness of 20 during lateral growth of 20 between trench 16 and over dielectric 14 such that thickness of 20 is greater than or equal to 200 nm, with routine experiment and optimization, since the lateral thickness of 20 is important, in order to include divots at the location of merged lateral growth fonts, as taught by Adusumilli above. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Allowable Subject Matter
Claims 5-7, 9-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
With respect to claims 5 & 9, the prior art of record does not appear to teach, suggest, or provide motivation for combination to following limitation:
further comprising: an opening that penetrates at least partially through the first semiconductor layer and through the second semiconductor layer,wherein the second section of the first semiconductor layer is laterally disposed between the opening and the shallow trench isolation region (claim 5)
further comprising:a second dielectric layer over the first section of the second semiconductor layer,wherein the second semiconductor layer includes a second section over the second dielectric layer, and the second section of the second semiconductor layer comprises a single- crystal semiconductor material (claim 9)
Claim 6-7 are objected to being dependent on claim 5.
Claim 10-16 are objected to being dependent on claim 9.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHATIB A RAHMAN whose telephone number is (571)270-0494. The examiner can normally be reached on MON-FRI 8:00 am- 5:00 pm (Arizona).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Steven Loke, can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.A.R/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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