Prosecution Insights
Last updated: October 01, 2026
Application No. 18/421,026

SEMICONDUCTOR DIE AND WAFER BONDING CRACK DETECTOR STRUCTURES AND METHODS OF FORMING SAME

Non-Final OA §102§103
Filed
Jan 24, 2024
Examiner
ANYA, IGWE U
Art Unit
2891
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
817 granted / 961 resolved
+17.0% vs TC avg
Minimal -4% lift
Without
With
+-3.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
26 currently pending
Career history
970
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
51.1%
+11.1% vs TC avg
§102
36.6%
-3.4% vs TC avg
§112
6.9%
-33.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 961 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 8, 10 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Funaki et al. (US 2023/0187430). PNG media_image1.png 535 365 media_image1.png Greyscale (Claim 1) Funaki teaches a semiconductor structure comprising: a first semiconductor die or wafer (120) including a first bonding crack detection structure portion (130), the first bonding crack detection structure portion (130) including a first set of metal bond pads (130, left) operatively connected to a bonding interface side (fig. 20 #114) of the first semiconductor die or wafer and a second set of metal bond pads (130, right) operatively connected to the bonding interface side (114) of the first semiconductor die or wafer (120), the second set of metal bond pads (130, right) electrically isolated (connected to different #132) from the first set of metal bond pads (130, left); a second semiconductor die or wafer (100) bonded to the first semiconductor die or wafer (120), the second semiconductor die or wafer (100) including a second bonding crack detection structure portion (108) that is bonded to the first bonding crack detection structure portion (130), the second bonding crack detection structure portion (108) including a third set of metal bond pads (108, left) operatively connected to a bonding interface side (104) of the second semiconductor die or wafer (100) and a fourth set of metal bond pads (108 right) operatively connected to the bonding interface side of the second semiconductor die or wafer, the fourth set of metal bond pads (104 right) electrically isolated from the third set of metal bond pads (104 left), wherein the first bonding crack detection structure portion (130) and the second bonding crack detection structure (108) portion are bonded together to form a bonding crack detection structure in which the first set of metal bond pads (130, left) and the third set of metal bond pads (108, left) are electrically connected together, and the second set of metal bond pads (130 right) and the fourth set of metal bond pads (108 right) are electrically connected together. (Claim 8) Funaki teaches wherein the metal bond pads (108, 130) are circular shaped, oval shaped or polygonal shaped (figs. 2, 4). (Claim 10) Funaki teaches a semiconductor structure comprising: a first semiconductor wafer (120) including a first bonding crack detection structure portion (130), the first bonding crack detection structure portion (130) including a first set of metal bond pads (130 left) operatively connected to a bonding interface side of the first semiconductor wafer and a second set of metal bond pads (130 right) operatively connected to the bonding interface side of the first semiconductor wafer, the second set of metal bond pads (130 right) electrically isolated from the first set of metal bond pads (130 left); a second semiconductor wafer (100) bonded to the first semiconductor wafer (120), the second semiconductor wafer (100) including a second bonding crack detection structure portion (108) that is bonded to the first bonding crack detection structure portion (130), the second bonding crack detection structure portion (108) including a third set of metal bond pads (108 left) operatively connected to a bonding interface side of the second semiconductor wafer and a fourth set of metal bond pads (108 right) operatively connected to the bonding interface side of the second semiconductor wafer, the fourth set of metal bond pads (108 right) electrically isolated from the third set of metal bond pads (108 left), wherein the first bonding crack detection structure portion (130) and the second bonding crack detection structure portion (108) are bonded together to form a bonding crack detection structure in which the first set of metal bond pads (130 left) and the third set of metal bond pads (108 left) are electrically connected together, and the second set of metal bond pads (130 right) and the fourth set of metal bond pads (108 right) are electrically connected together. (Claim 17) Funaki teaches wherein the metal bond pads (108, 130) are circular shaped, oval shaped or polygonal shaped (figs. 2, 4). Claims 21 – 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kwon et al. (US 2024/0258180). PNG media_image2.png 318 516 media_image2.png Greyscale (Claim 21) kwon et al. teach a semiconductor structure comprising: a first semiconductor die or wafer (L3) including a first bonding crack detection structure portion (BP3); and a second semiconductor die or wafer (L2) bonded to the first semiconductor die or wafer (L3), the second semiconductor die or wafer (L2) including a second bonding crack detection structure portion (BP2) that is bonded to the first bonding crack detection structure portion (BP3), wherein the first bonding crack detection structure portion and the second bonding crack detection structure portion are configured to form a bonding crack detection structure and the bonding crack detection structure is configured to have a measurable electrical characteristic indicating a presence of an absence of a bonding crack and a presence of a bonding crack (paragraphs 69 – 72). (Claim 22) Kwon et al. teach wherein the measurable electrical characteristic is an electrical current flowing between the first bonding crack detection structure portion and the second bonding crack detection structure portion (paragraphs 69 – 72). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 2, 9, 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Funaki et al. (US 2023/0187430) in view of Pachamuthu et al. (US 2022/0108926). (Claim 2) Funaki lacks wherein the bonding crack detection structure comprises a capacitor including: a first conductor of the capacitor comprising the first set of metal bond pads and the third set of metal bond pads which are electrically connected together; and a second conductor of the capacitor comprising the second set of metal bond pads and the fourth set of metal bond pads which are electrically connected together; and an insulator of the capacitor comprising a gap between the first conductor of the capacitor and the second conductor of the capacitor. However, Pachamuthu et al. teach wherein the bonding crack detection structure comprises a capacitor including: a first conductor (103) of the capacitor comprising the first set of metal bond pads and the third set of metal bond pads (101) which are electrically connected together; and a second conductor (102) of the capacitor comprising the second set of metal bond pads and the fourth set of metal bond pads (100) which are electrically connected together; and an insulator of the capacitor comprising a gap (58) between the first conductor of the capacitor and the second conductor of the capacitor (paragraph 19) for the benefit of the benefit of detecting a crack at the edge seal (paragraph 18). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of the benefit of detecting a crack at the edge seal. (Claim 9) Funaki lacks wherein the bonding crack detection structure is located along one or more edges of the semiconductor structure, or one or more edges of the first semiconductor die or wafer and the second semiconductor die or wafer. However, Pachamuthu et al. teach wherein the bonding crack detection structure is located along one or more edges of the semiconductor structure, or one or more edges of the first semiconductor die or wafer and the second semiconductor die or wafer (paragraph 19) for the benefit of the benefit of detecting a crack at the edge seal (paragraph 18). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of the benefit of detecting a crack at the edge seal. (Claim 11) Funaki lacks wherein the bonding crack detection structure comprises a capacitor including: a first conductor of the capacitor comprising the first set of metal bond pads and the third set of metal bond pads which are electrically connected together; and a second conductor of the capacitor comprising the second set of metal bond pads and the fourth set of metal bond pads which are electrically connected together. However, Pachamuthu et al. teach wherein the bonding crack detection structure comprises a capacitor including: a first conductor (103) of the capacitor comprising the first set of metal bond pads and the third set of metal bond pads (101) which are electrically connected together; and a second conductor (102) of the capacitor comprising the second set of metal bond pads and the fourth set of metal bond pads (100) which are electrically connected together (paragraph 19) for the benefit of the benefit of detecting a crack at the edge seal (paragraph 18). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of the benefit of detecting a crack at the edge seal. (Claim 18) Funaki lacks wherein the bonding crack detection structure is located along one or more edges of the semiconductor structure, one or more edges of a plurality of dies located on the first semiconductor wafer and second semiconductor wafer, or in one or more scribe lines of the first semiconductor wafer and second semiconductor wafer. However, Pachamuthu et al. teach wherein the bonding crack detection structure is located along one or more edges of the semiconductor structure, one or more edges of a plurality of dies located on the first semiconductor wafer and second semiconductor wafer, or in one or more scribe lines of the first semiconductor wafer and second semiconductor wafer(paragraph 19) for the benefit of the benefit of detecting a crack at the edge seal (paragraph 18). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of the benefit of detecting a crack at the edge seal. Allowable Subject Matter Claims 3 – 7 and 12 – 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Prior art made of record and not relied upon, considered pertinent to applicant's disclosure are listed in PTO – 892 Form. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to IGWE U ANYA whose telephone number is (571)272-1887. The examiner can normally be reached 8:00 AM - 6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272- 1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /IGWE U ANYA/Primary Examiner, Art Unit 2891 September 5, 2026
Read full office action

Prosecution Timeline

Jan 24, 2024
Application Filed
Sep 10, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
81%
With Interview (-3.7%)
2y 6m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 961 resolved cases by this examiner. Grant probability derived from career allowance rate.

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