CTNF 18/421,096 CTNF 101406 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions 08-06 AIA Claim s 16-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention , there being no allowable generic or linking claim. Election was made without traverse in the reply filed on May 15, 2026 . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-7, 9-15, 21-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiang et al. (US 20220131017 A1) and Huang et al (US 20220238730 A1) . Regarding claim 1 , Chiang discloses a method for forming a semiconductor device structure, comprising: forming a p-type doped region (518) and an n-type doped region (510) in a semiconductor substrate (300, Fig. 13); partially removing the semiconductor substrate to form a recess (1302, trench structure, Fig. 13) exposing portions of the p-type doped region (518, trench exposes structure, Fig. 13) and the n-type doped region (510, trench exposes structure, Fig. 13); forming a photo-sensing structure (309, Fig. 17) over sidewalls and a bottom of the recess; and forming a semiconductor cap (526, Fig. 17) over the photo-sensing structure. Chiang does not disclose wherein the semiconductor cap is p-type doped. However, Huang discloses the semiconductor cap is p-typed doped (paragraph 23). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chiang in view of Huang such that the semiconductor cap is p-typed doped. Doing so enables low-resistance ohmic metal contacts and create a strong built-in electric field. Regarding claim 2 , Chiang discloses the photo-sensing structure and the semiconductor cap are epitaxially grown in-situ in a process chamber, and vacuum of the process chamber is not broken during the growth of photo- sensing structure and the semiconductor cap (paragraph 38). Regarding claim 3 , Chiang discloses epitaxial growing a silicon germanium layer (1502, Fig. 15A) on the photo-sensing structure before the formation of the semiconductor cap (paragraph 39). Regarding claim 4 , Chiang discloses the silicon germanium layer has an atomic concentration of germanium, and the atomic concentration of germanium gradually decreases along a direction from a bottom of the silicon germanium layer towards the semiconductor cap (paragraph 30, percentage of germanium decreases from bottom to top). Regarding claim 5 , Chiang discloses forming a nitrogen-containing stressor layer (530, paragraph 27) over the semiconductor cap (526, Fig. 18). Regarding claim 6 , Chiang discloses the nitrogen-containing stressor layer (530) extends past opposite edges of the photo-sensing structure (Fig. 17/18, layer 530 extends past photo-sensing structure 309). Regarding claim 7 , Chiang does not disclose the semiconductor cap is a silicon layer doped with p-type dopants. However, Huang discloses the semiconductor cap (18) is a silicon layer doped with p-type dopants (paragraph 23). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chiang in view of Huang such that the semiconductor cap is p-typed doped. Doing so enables low-resistance ohmic metal contacts and create a strong built-in electric field. Regarding claim 9 , Chiang discloses the p-type doped region (518) and the n-type doped region (510) are partially removed during the formation of the recess (Fig. 13, upper left and right corners are removed during formation of the trench 1302). Regarding claim 10 , Chiang discloses the photo-sensing structure (309) is formed to be protruding from a top surface of the semiconductor substrate (300) (photo-sensing structure 309 is protruding from substrate 300 in Fig. 17). Regarding claim 11 , a method for forming a semiconductor device structure, comprising: forming a p-type doped structure (518) and an n-type doped structure (510); forming a photo-sensing structure (309), wherein a portion of the photo-sensing structure is between the p-type doped structure and the n-type doped structure (Fig. 5A); and forming a semiconductor cap over the photo-sensing structure (526). However, Chiang does not disclose wherein the semiconductor cap is p-type doped. On the other hand, Huang discloses the semiconductor cap is p-type doped (paragraph 23). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chiang in view of Huang such that the semiconductor cap is p-typed doped. Doing so enables low-resistance ohmic metal contacts and create a strong built-in electric field. Regarding claim 12 , Chiang discloses the semiconductor cap (526) is formed directly on the photo-sensing structure (309, Fig. 5A). Regarding claim 13 , Chiang discloses the edges of the semiconductor cap (526) and the photo-sensing structure (309) are vertically aligned with each other (Fig. 5A). Regarding claim 14 , Chiang discloses forming a dielectric protective element (530) over the semiconductor cap (526), wherein the dielectric protective element extends past a first interface between the photo-sensing structure and the p-type doped structure (left edge of 530 extends past 518) and a second interface between the photo-sensing structure and the n-type doped structure (right edge of 530 extends past 510). Regarding claim 15 , forming a first conductive structure (318, Fig. 19) electrically connected to the p-type doped structure (516); and forming a second conductive structure (320) electrically connected to the n-type doped structure (508). Regarding claim 21 , Chiang discloses a method for forming a semiconductor device structure, comprising: forming a first doped structure (518) and a second doped structure (510, Fig. 17); forming a photo-sensing structure (309, Fig. 17), wherein a portion of the photo-sensing structure is between the first doped structure and the second doped structure (309 is between 518 and 510, Fig. 17); and forming a semiconductor cap over the photo-sensing structure (526, Fig. 17). However, Chiang does not disclose wherein the semiconductor cap contains p-type dopants. On the other hand, Huang discloses wherein the semiconductor cap contains p-type dopants (paragraph 23). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chiang in view of Huang such that the semiconductor cap is p-typed doped. Doing so enables low-resistance ohmic metal contacts and create a strong built-in electric field. Regarding claim 22 , Chiang discloses forming a recess (1302) exposing the first doped (518) structure and the second doped structure (510) before the photo-sensing structure is formed (Fig. 13). Regarding claim 23 , Chiang discloses the first doped structure (518) and the second doped structure (510) are partially removed while the recess is formed (Fig. 13, upper corners of 518 and 510 are removed during formation of trench). Regarding claim 24 , Chiang discloses forming a dielectric protective element (530) over the semiconductor cap (526), wherein the dielectric protective element extends across opposite sidewalls of the photo-sensing structure (309, Fig. 18) (paragraph 27). Regarding claim 25 , Chiang discloses the dielectric protective element (530) has a first edge (left edge of 530, Fig. 18) and a second edge (right edge of 530, Fig. 18), the first doped structure (520) laterally extends across the first edge of the dielectric protective element, and the second doped structure (512) laterally extends across the second edge of the dielectric protective element (Fig. 18) . 07-21-aia AIA Claim (s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiang et al. (US 20220131017 A1) and Huang et al (US 20220238730 A1) as applied to claim 1 above, in further view of Taguchi et al (US 20250318286 A1) . Regarding claim 8 , neither Chiang nor Huang disclose the semiconductor cap has a p-type dopant concentration that is within a range from about 10sup17cm-3 to about 10sup19cm-3. However, Taguchi discloses the semiconductor cap has a p-type dopant concentration that is within a range from about 10sup17cm-3 to about 10sup19cm-3 (paragraph 56). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chiang and Huang in view of Taguchi such that the semiconductor cap has a p-type dopant concentration that is within a range from about 10sup17cm-3 to about 10sup19cm-3. Doing so would optimize device performance by improving contact resistance reduction and creating a strong built-in electric field. Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE Q PHAN whose telephone number is (571)272-1227. The examiner can normally be reached Monday - Friday 8am - 5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (571) 272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STEVE PHAN/Examiner, Art Unit 2817 /MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817 Application/Control Number: 18/421,096 Page 2 Art Unit: 2817 Application/Control Number: 18/421,096 Page 3 Art Unit: 2817 Application/Control Number: 18/421,096 Page 4 Art Unit: 2817 Application/Control Number: 18/421,096 Page 5 Art Unit: 2817 Application/Control Number: 18/421,096 Page 6 Art Unit: 2817 Application/Control Number: 18/421,096 Page 7 Art Unit: 2817 Application/Control Number: 18/421,096 Page 8 Art Unit: 2817
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