DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-15 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tada et al. (20010048122) in view of Yamaji (20140217466)
Regarding Claim 1, in Figs 3 and 4 and paragraphs 0018, 0019, 0025, 0082, 0087, 0120 and 0126 Tada discloses a method for manufacturing a device, the method comprising: forming a shielding structure 10 (see paragraph 0025) for a high voltage semiconductor device; forming a high voltage interconnection 12/13 that connects to a first (right) portion of the shielding structure 10 and to a first terminal associated with a drain region 6 of the hv semiconductor device; and forming a metal routing 13 that connects a second (left) portion of the shielding structure 10 and a second terminal associated with a source region 25 of the hv semiconductor device. Tada et fails to disclose the device to be ultra-high voltage device rather than high voltage device. However, Yamaji discloses a semiconductor device where Figs. 1, 2, 4 and 5 and in paragraph 0005, 0008, 0012, 0148, 0150 and 0172 the required ultra-high voltage device is disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed in invention to have the required ultra-high voltage device rather than high voltage device in Tada et al. as taught by Yamaji in order to be able to use the device in industrial applications.
Regarding Claim 2, Tada et al. discloses forming the shielding structure includes forming a winding-type polysilicon material 10. (Please note that “implant” polysilicon material is disclosed in paragraph 0047, 0116 and 0117 of Yamaji).
Regarding Claim 3, in Tada et al, in Figs. 3 and 4, forming the shielding structure includes forming a single winding polysilicon line 10 with a first end (left) that connects to the source region 25 and a second (right) end that connects to the drain region 6.
Regarding Claim 4, in Fig 3 of Tada eta l. forming the shielding structure 10 includes forming a single winding polysilicon line with one or more U-turns.
Regarding Claim 5, in Figs 3 and 4 of Tada et al,,the shielding structure 10 includes forming two winding polysilicon lines.
Regarding Claim 6, in Figs. 3 and 4 of Tada et al. forming the shielding structure 10 includes forming four winding polysilicon lines.
Regarding Claim 6, in Figs. 3 and 4 of Tada et al, doping an oxide layer 8 of the device to form a source contact 25/p+, a drain contact 6, and a central contact (see paragraph 0075, 0087)(Please also note that the high side driver contact as shown in Fig. 1 of Yamaji also could be considered a central contact)
Regarding Claim 8, in Figs 3 and 4 and paragraphs 0018, 0019, 0025, 0082, 0087, 0120 and 0126 Tada discloses a high voltage (HV) semiconductor device, comprising: a source region 25/p+; a drain region 6; a shielding structure 10; a high voltage interconnection 12/31 coupled to a first (right) portion of the shielding structure 10 and to a first terminal associated with the drain region 6; and a metal routing 12/31 that couples a second (left) portion of the shielding structure 10 and a second terminal 31 associated with the source region 25/p+. Tada et fails to disclose the device to be ultra-high voltage device rather than high voltage device. However, Yamaji discloses a semiconductor device where Figs. 1, 2, 4 and 5 and in paragraph 0005, 0008, 0012, 0148, 0150 and 0172 the required ultra-high voltage device is disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed in invention to have the required ultra-high voltage device rather than high voltage device in Tada et al. as taught by Yamaji in order to be able to use the device in industrial applications.
Regarding Claim 9, the shielding structure 10 includes a winding-type polysilicon material. (Please note that “implant” polysilicon material is disclosed in paragraph 0047, 0116 and 0117 of Yamaji).
Regarding Claim 10, in Figs 3 and 4 of Tada et al, the shielding structure 10 includes a single winding polysilicon line with a first end that connects to the source region 25/p+ and a second end that connects to the drain region 6.
Regarding Claim 11, in Figs. 3 and 4 of Tada et al, the shielding structure 10 includes a single winding polysilicon line with one or more U-turns.
Regarding Claim 12, in Figs. 3 and 4, the shielding structure 10 includes two winding polysilicon lines.
Regarding Claim 13, in Figs. 3 and 4, the shielding structure 10 includes four winding polysilicon lines.
Regarding Claim 14, in Figs. 3 and 4 of Tada et al, doping an oxide layer 8 of the device to form a source contact 25/p+, a drain contact 6, and a central contact (see paragraph 0075, 0087)(Please also note that the high side driver contact as shown in Fig. 1 of Yamaji also could be considered a central contact)
Regarding Claim 15, in Figs 3 and 4 and paragraphs 0018, 0019, 0025, 0082, 0087, 0120 and 0126 Tada discloses a method for manufacturing a device, the method comprising: providing an high voltage (HV) component that includes a source region 25/p+ and a drain region 6; forming a shielding structure 10 above the drain region; forming a high voltage interconnection 12/31 that connects to a first (right) portion of the shielding structure 10 and to a first terminal associated with the drain region 6; and forming a metal routing 12/31 that connects a second (left) portion of the shielding structure 10 and a second terminal associated with the source region 25/p+. Tada et fails to disclose the device to be ultra-high voltage device rather than high voltage device. However, Yamaji discloses a semiconductor device where Figs. 1, 2, 4 and 5 and in paragraph 0005, 0008, 0012, 0148, 0150 and 0172 the required ultra-high voltage device is disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed in invention to have the required ultra-high voltage device rather than high voltage device in Tada et al. as taught by Yamaji in order to be able to use the device in industrial applications.
Regarding Claim 17, in Figs. 3 and 4 of Tada et al, doping an oxide layer 8 of the device to form a source contact 25/p+, a drain contact 6, and a central contact (see paragraph 0075, 0087)(Please also note that the high side driver contact as shown in Fig. 1 of Yamaji also could be considered a central contact)
Regarding Claim 18, in Figs. 1-4 of Yamaji, connecting a third terminal (i.e. for example an OUT terminal) to a central region of the device (i.e. high side driver, please see paragraph 0010, 0029, 0030 and 0088)
Regarding Claim 19, in Figs. 3 and 4 of Tada et al., the shielding structure 10 includes one of: a single winding polysilicon line, two winding polysilicon lines, or four winding polysilicon lines.
Regarding Claim 20, in Figs. 3 and 4 of Tada et al, the shielding structure 10includes a single winding polysilicon line with one or more U-turns.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Tada et al. (20010048122) in view of Yamaji (20140217466) as applied above further in view of Yamaji (20120286829).
Regarding Claim 16, in combination Tada et al. and Yamaji (‘466) discloses everything except to disclose the required gate poly structure. However, Yamaji ‘829 discloses a semiconductor device and associated driving circuitry where in paragraph 0059, 0136, 0189 and 0195 the required gate poly structure is disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required gate poly in Tada et al. and Yamaji (‘466) combination as taught by Yamaji (‘829) in order to have increased breakdown voltage.
Cited Prior Art That Are NOT Relied Upon
Examiner is including Karino et al. (20170207296) (paragraphs 0044, 0050, 0063, 0093) and Huo et al. (20150262995) (paragraph 0030) as pertinent prior arts that are NOT relied upon on this rejection but that do disclose spiral/winding polysilicon resistance/field plate structure for high voltage applications
Conclusion
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 3/7/2026