Attorney’s Docket Number: KAII-2024065p
Filing Date: 01/24/2024
Claimed Foreign Priority Date: 12/11/2023 (KR10-2023-0178517)
Inventors: Cho et al.
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the amendments filed on 6/15/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Acknowledgement
The Amendment filed on 6/15/2025, responding to the Office action mailed 5/01/2026, has
been entered. Applicant amended claims 2, 6, 8-9, 11, and 14-16. Applicant cancelled claims 1 and 10. The present Office action is made with all the suggested amendments being fully considered.
Response to Amendments
Applicant’s amendments to the claims have failed to overcome the claim rejections under 35 U.S.C. 112, but have overcome the claim rejections of 35 U.S.C. 103 as previously formulated in the Non-Final Office action mailed on 5/01/2026. Accordingly, pending in this application are claims 2-9 and 11-20. New grounds of rejection are presented below, however, as necessitated by applicant’s amendments to the claims and upon further search/consideration.
Claim Objections
Claim 3 is objected to because of the following informalities: “…wherein peripheral body diode region…” is improper. For the purposes of examination, the line will be construed to recite “…wherein the first peripheral body diode region…”. Appropriate correction is required.
Claim 8 is objected to because of the following informalities: “…the second peripheral body diode region extends to a distal end of region” is improper. For the purposes of examination, the line will be construed to recite “…the second peripheral body diode region extends to a distal end of the first region”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 16 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 recites the limitation "the first direction" in line 8. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “the first direction” within line 8 will be construed to recite “a first direction”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 4, 5-9, 11-12 and 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Nakashima (US 20240162344 A1) in view of Fukutani (US 20240072045 A1) further in view of Hoki (US 20170084693 A1).
Regarding claim 2, Nakashima (see, e.g., figs. 7-8) shows most aspects of the instant invention, including a semiconductor device (e.g., semiconductor device 10A) comprising:
A substrate (e.g., third metal layer 19);
An active cell region (e.g., cell region 60, see green-striped region in annotated fig. 1 below) comprising a first active region (e.g., first active region of annotated fig. 1 below) including a recessed region (e.g., see, e.g., recessed geometry of cell region 60 around recess 14) and a second active region (e.g., second active region of annotated fig. 1 below) on the substrate (e.g., third metal layer 19);
An edge terminal region (e.g., gate electrode 16 + paragraph 28 “The portion of the gate electrode 16 exposed through the second pad opening 11B functions as an external terminal…”) surrounding the active cell region (e.g., cell region 60) on the substrate (e.g., third metal layer 19);
A first peripheral region (e.g., source electrode 13 region left of black division bar, see annotated fig. 1) comprising a first region (e.g., edge portion of source electrode 13 in recess 14 area) within the recessed region (e.g., note that source electrode 13 forms the recess 14 that recesses into the cell region 60) and a second region (e.g., portion of source electrode 13 area between recess 14 and top left corner of fig. 7) disposed between the first active region (e.g., first active region of annotated fig. 1 below) and the edge terminal region (e.g., gate electrode 16 + paragraph 28 “The portion of the gate electrode 16 exposed through the second pad opening 11B functions as an external terminal…”) on the substrate (e.g., third metal layer 19);
A second peripheral region (e.g., source electrode 13 region right of black division bar, see annotated fig. 1) disposed between the second active region (e.g., second active region of annotated fig. 1 below) and the edge terminal region (e.g., gate electrode 16 + paragraph 28 “The portion of the gate electrode 16 exposed through the second pad opening 11B functions as an external terminal…”);
A first gate electrode (e.g., gate electrode 66) disposed on the substrate (e.g., third metal layer 19) in the first active region (e.g., first active region of annotated fig. 1 below);
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Annotated Fig. 1
Nakashima (see, e.g., fig. 7), however, fails to explicitly show a first body diode region extending from the second region of the first peripheral region to a portion of the first active region, wherein the first body diode region comprises: a first peripheral body diode region disposed in the second region; and a second peripheral body diode region extending from the first peripheral body diode region and extending below the first gate electrode, while it also fails to show a first pillar structure disposed within the substrate, disposed over a portion of the second region and the first active region, and disposed below the first body diode region; and a second pillar structure disposed within the substrate and disposed to be spaced apart from the first pillar structure in the first active region, wherein the first pillar structure comprises: a first pillar region extending into the substrate from the first peripheral body diode region in the second region; and a second pillar region extending into the substrate from the second peripheral body diode region in the first active region, and the second pillar structure extends into the substrate from a first body region below a second gate electrode disposed on the substrate in the first active region.
Fukutani (see, e.g., figs. 4-5), in a similar device to Nakashima, teaches a first body diode region (e.g., diode region 45d stack) extending across an active cell region from a peripheral/corner region (see, e.g., pad beside region 452a formed by the recess with individual 45d portion) to a portion of a region within a recessed region (e.g., recessed geometry of fig. 4), wherein the first body diode region (e.g., diode region 45d stack) comprises: a first peripheral body diode region (see, e.g., annotated fig. 2 below) disposed in a second region (e.g., region extending from recess portion to top left corner region), and a second peripheral body diode region (e.g., remaining diode 45 region stack) extending from the first peripheral body diode region (see, e.g., annotated fig. 2 below) and extending below (e.g., note that diode region 45d is configured with a structure portion beneath the gate electrode, see fig. 5 and paragraph 75) a first gate electrode (e.g., gate electrode 55) disposed on a substrate (e.g., substrate 41) in a first active region (e.g., active region 45).
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Annotated Fig. 2
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the first body diode region configuration and extension portion under the first gate electrode configuration of Fukutani within the peripheral/active cell region layout of Nakashima, in order to provide improved performance and component density within the device while simultaneously increasing the recovery capacity benefits within the device due to the reverse biased state configuration (see, e.g., paragraph 102 of Fukutani).
Nakashima in view of Fukutani, however, fails to explicitly teach a first pillar structure disposed within the substrate, disposed over a portion of the second region and the first active region, and disposed below the first body diode region; and a second pillar structure disposed within the substrate and disposed to be spaced apart from the first pillar structure in the first active region, wherein the first pillar structure comprises: a first pillar region extending into the substrate from the first peripheral body diode region in the second region; and a second pillar region extending into the substrate from the second peripheral body diode region in the first active region, and the second pillar structure extends into the substrate from a first body region below a second gate electrode disposed on the substrate in the first active region.
Hoki (see, e.g., fig. 2), in a similar device to Nakashima in view of Fukutani, teaches a first pillar structure (e.g., left-most p type column layer 14 + centered p type column layer 14 + second p type column layer 14 between left-most and centered p type column layers + p type guard ring 11 adjacent to left-most p type column layer) disposed within a substrate (e.g., semiconductor substrate 2), disposed over a portion of a second region (e.g., n type base layer 13) and a first active region (e.g., active region 3), and a second pillar structure (e.g., edge p type guard ring 11) disposed within the substrate (e.g., semiconductor substrate 2) and disposed to be spaced apart from the first pillar structure (e.g., left-most p type column layer 14 + centered p type column layer 14 + second p type column layer 14 between left-most and centered p type column layers + p type guard ring 11 adjacent to left-most p type column layer) disposed within a substrate (e.g., semiconductor substrate 2) in the first active region (e.g., active region 3), wherein the first pillar structure (e.g., left-most p type column layer 14 + centered p type column layer 14 + second p type column layer 14 between left-most and centered p type column layers) disposed within a substrate (e.g., semiconductor substrate 2) comprises: a first pillar region (e.g., left-most p type column layer 14) extending into the substrate (e.g., semiconductor substrate 2) from the second region (e.g., n type base layer 13); and a second pillar region (e.g., centered p type column layer + p type column layer 14) extending into the substrate (e.g., semiconductor substrate 2) in the first active region (e.g., active region 3), and the second pillar structure (e.g., edge p type guard ring 11) extends into the substrate (e.g., semiconductor substrate 2) from a first body region (e.g., parasitic diode 25) below a second gate electrode (e.g., gate electrode 18) disposed on the substrate (e.g., semiconductor substrate 2) in the first active region (e.g., active region 3).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the first and second pillar structure of Hoki within the active/peripheral region of Nakashima in view of Fukutani, in order to achieve the expected result of extending providing additional current support for the peripheral body diode region within the device. Note that the second peripheral body diode region is spaced vertically above the second pillar region, so including the second pillar region in this configuration would result in a vertically extending arrangement from the second peripheral body diode region as disposed in the first active region.
Regarding claim 4, Hoki (see, e.g., figs 1-2) teaches wherein the first pillar structure (e.g., left-most p type column layer 14 + centered p type column layer 14 + second p type column layer 14 between left-most and centered p type column layers + p type guard ring 11 adjacent to left-most p type column layer) further comprises a third pillar region (e.g., second p type column layer 14, between the left-most and centered most p type column layers + p type guard ring 11) between the first pillar region (e.g., left-most p type column layer 14) and the second pillar region (e.g., centered p type column layer 14), and connecting (e.g., note that the third pillar region is disposed directly between the first and second pillar regions, so it electrically connects the two) an upper part of the first pillar region (e.g., left-most p type column layer 14) and an upper part of the second pillar region (e.g., centered p type column layer 14).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the third pillar region of Hoki within the first pillar structure of Nakashima in view of Fukutani further in view of Hoki, in order to achieve the expected result of expanding the pillar support for the current-flow profile within the device.
Regarding claim 5, Nakashima in view of Fukutani further in view of Hoki teaches wherein the first body region (e.g., parasitic diode 25 of Hoki) and the first body diode region (e.g., diode region 45d stack of Fukutani) are spaced apart from each other (see, e.g., Fukutani and Hoki modifications as argued within claim 2).
Hoki (see, e.g., figs. 1-2) teaches wherein the first body region (e.g., parasitic diode 25) is spaced apart from a second body region (e.g., n type drain layer 12) that is disposed within the substrate (e.g., semiconductor substrate 2) in the first active region (e.g., active region 3) and disposed below the second gate electrode (e.g., gate electrode 18).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the second body region and spacing configuration of Hoki within the device of Nakashima in view of Fukutani further in view of Hoki, in order to achieve the expected result of providing epitaxial support beneath the pillar structure and peripheral diode region of the device.
Regarding claim 6, Nakashima (see, e.g., figs. 7-8) shows wherein the second region (e.g., portion of source electrode 13 area between recess 14 and top left corner of fig. 7) comprises: a first sub-region (e.g., source electrode 13 portion in top left of fig. 7, see annotated fig. 3) extending in a first direction (e.g., vertical direction of fig. 7) and disposed between the first active region (e.g., first active region of annotated fig. 3 below) and the edge terminal region (e.g., gate electrode 16 + paragraph 28 “The portion of the gate electrode 16 exposed through the second pad opening 11B functions as an external terminal…”), a second sub-region (e.g., extending source electrode 13 portion, see annotated fig. 3 below) extending in a second direction (e.g., horizontal direction) intersecting the first direction (e.g., vertical direction), and being between the first region (e.g., edge portion of source electrode 13 in recess 14 area) and the edge terminal region (e.g., gate electrode 16 + paragraph 28 “The portion of the gate electrode 16 exposed through the second pad opening 11B functions as an external terminal…”), a third sub-region (e.g., sub-region of source electrode 13 between first sub-region and second sub-region, see annotated fig. 3 below) extending (e.g., note the third sub-region has a width extending in the horizontal direction) in the second direction (e.g., horizontal direction), and disposed between the first sub-region (e.g., source electrode 13 portion in top left of fig. 7, see annotated fig. 3) and the second sub-region (e.g., extending source electrode 13 portion, see annotated fig. 3 below) and between the first active region (e.g., first active region of annotated fig. 3 below) and the edge terminal region (e.g., gate electrode 16 + paragraph 28 “The portion of the gate electrode 16 exposed through the second pad opening 11B functions as an external terminal…”).
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Annotated Fig. 3
Fukutani (see, e.g., figs. 4-5) teaches wherein the body diode region (e.g., diode region 45d stack) extends from a third sub-region (e.g., third sub-region of annotated fig. 4) of the second region to a portion of the first active region (e.g., active region 45), and the first peripheral body diode region (see, e.g., annotated fig. 2 above, alternate annotations of same embodiment) is disposed in the third sub-region (e.g., third sub-region of annotated fig. 4).
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Annotated Fig. 4
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the body diode region sub-region extension setup of Fukutani within the configuration of Nakashima in view of Fukutani further in view of Hoki, in order to achieve the expected result of utilizing the entire span of the sub-region for the space of the diode stack.
Regarding claim 7, Nakashima (see, e.g., figs. 7-8) shows wherein the third sub-region (e.g., sub-region of source electrode 13 between first sub-region and second sub-region, see annotated fig. 3 above) does not overlap the first region (e.g., edge portion of source electrode 13 in recess 14 area) along the first direction (e.g., vertical direction).
Regarding claim 8, Nakashima (see, e.g., figs. 7-8) shows wherein the first region (e.g., edge portion of source electrode 13 in recess 14 area, see annotated fig. 7 above) protrudes along a first direction from the second region (e.g., portion of source electrode 13 area between recess 14 and top left corner of fig. 7).
Fukutani (see, e.g., figs. 4-5) teaches the second peripheral body diode region (e.g., diode region 45d stack) extends to a distal end (see, e.g., full span of diode region 45d stack, noting it extends across the entire active cell region, including past the recess area) of the first region (e.g., note that the diode region 45d extends over and between the entire cell region of Fukutani, including from the recess edge to the corner regions).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the peripheral body diode extension configuration of Fukutani within the setup of Nakashima in view of Fukutani further in view of Hoki, in order to achieve the expected result of utilizing the full span near the recess for additional diode space, further improving the recovery capacity benefits within the device.
Regarding claim 9, Fukutani (see, e.g., figs. 4-5) teaches a second body diode region (e.g., extending diode bodies past green-bar of annotated fig. 2 above) extending from the second peripheral region (e.g., second peripheral region of annotated fig. 2 above) to a portion of the second active region (e.g., active cell region right of green-bar, see annotated fig. 2 above).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the second body diode extension configuration of Fukutani within the second peripheral region and second active region setup of Nakashima in view of Fukutani further in view of Hoki, in order to achieve the expected result of utilizing the peripheral and active region space for the diode stack and its aforementioned recovery capacity improvements.
Regarding claim 11, Nakashima (see, e.g., figs. 7-8) shows most aspects of the instant invention, including a semiconductor device (e.g., semiconductor device 10A) comprising:
A substrate (e.g., third metal layer 19) comprising an active cell region (e.g., cell region 60, see green-striped region in annotated fig. 1 above), an edge terminal region (e.g., gate electrode 16 + paragraph 28 “The portion of the gate electrode 16 exposed through the second pad opening 11B functions as an external terminal…”) surrounding the active cell region (e.g., cell region 60), and a peripheral region (e.g., source electrode 13 region) between the active cell region (e.g., cell region 60, see green-striped region in annotated fig. 1 above) and the edge terminal region (e.g., gate electrode 16 + paragraph 28 “The portion of the gate electrode 16 exposed through the second pad opening 11B functions as an external terminal…”);
Nakashima (see, e.g., fig. 7), however, fails to explicitly show a peripheral body diode region disposed on the substrate, wherein the first body diode region comprises: a first peripheral body diode region disposed in the second region; and a second peripheral body diode region extending from the first peripheral body diode region and extending below the first gate electrode, and a first pillar structure disposed within the substrate, disposed over a portion of the peripheral region and the active cell region, and disposed below the peripheral body diode region; and a second pillar structure extending from the first body region into the substrate and spaced apart from the first pillar structure, wherein the first pillar structure comprises: a first pillar region extending into the substrate from the peripheral body diode region in the peripheral region; and a second pillar region extending into the substrate from the peripheral body diode region in the active cell region.
Fukutani (see, e.g., figs. 4-5), in a similar device to Nakashima, teaches a peripheral body diode region (e.g., diode region 45d stack) disposed on a substrate (e.g., substrate 41) and disposed to extend to a portion of an active cell region (e.g., active region 45) in a peripheral region (see, e.g., pad beside region 452a formed by the recess with individual 45d portion), a first body region (see, e.g., right-side of black division bar, see annotated fig. 5 below) spaced apart from the peripheral body diode region (e.g., remaining diode 45 region stack) and disposed in the active cell region (e.g., active region 45), a first gate electrode (see, e.g., gate electrode 55, see annotated fig. 6) disposed on the peripheral body diode region (e.g., diode region 45d stack) in a portion of the active cell region (e.g., active region 45), and a second gate electrode (e.g., gate electrode 55, further down the diode region, noting that fig. 6 is only a partial and incomplete cross section of fig. 6) disposed on the first body region (see, e.g., right-side of black division bar, see fig. 5 below) of the active cell region (e.g., active cell region 45).
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Annotated Fig. 5
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Annotated Fig. 6
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the peripheral body diode region configuration and gate electrode of Fukutani within the peripheral/active cell layout of Nakashima, in order to provide improved performance and component density within the device while simultaneously increasing the recovery capacity benefits within the device due to the reverse biased state configuration (see, e.g., paragraph 102 of Fukutani).
Nakashima in view of Fukutani, however, fails to teach a first pillar structure disposed within the substrate, disposed over a portion of the peripheral region and the active cell region, and disposed below the peripheral body diode region; and a second pillar structure extending from the first body region into the substrate and spaced apart from the first pillar structure, wherein the first pillar structure comprises: a first pillar region extending into the substrate from the peripheral body diode region in the peripheral region; and a second pillar region extending into the substrate from the peripheral body diode region in the active cell region.
Hoki (see, e.g., fig. 2), in a similar device to Nakashima in view of Fukutani, teaches a first pillar structure (e.g., left-most p type column layer 14 + second p type column layer 14 between left-most and centered p type column layers + p type guard ring 11 adjacent to left-most p type column layer) disposed within the substrate (e.g., semiconductor substrate 2), disposed over a portion of a peripheral region (e.g., peripheral field region 6) and the active cell region (e.g., active region 3), and a second pillar structure (e.g., center p type column layer 14) extending from a first body region (e.g., center region of active region 3) into the substrate (e.g., semiconductor substrate 2) and spaced apart from the first pillar structure (e.g., left-most p type column layer 14 + second p type column layer 14 between left-most and centered p type column layers + p type guard ring 11 adjacent to left-most p type column layer), wherein the first pillar structure (e.g., left-most p type column layer 14 + centered p type column layer 14 + second p type column layer 14 between left-most and centered p type column layers + p type guard ring 11 adjacent to left-most p type column layer) comprises: a first pillar region (adjacent p type guard ring 11) extending into the substrate (e.g., semiconductor substrate 2) in the peripheral region (e.g., peripheral field region 6); and a second pillar region (e.g., second p type column layer 14) extending into the substrate (e.g., semiconductor substrate 2) in the active cell region (e.g., active region 3).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the first and second pillar structure of Hoki within the active/peripheral region of Nakashima in view of Fukutani, in order to achieve the expected result of extending providing additional current support for the peripheral body diode region within the device.
Regarding claim 12, Fukutani (see, e.g., figs. 4-5) teaches the peripheral body diode region (e.g., remaining diode 45 region stack) comprises: a first peripheral body diode region disposed in the peripheral region (see, e.g., pad beside region 452a formed by the recess with individual 45d portion), and a second peripheral body diode region (e.g., remaining peripheral diode portion) extending from the peripheral body diode region (e.g., remaining diode 45 region stack) and extending below (e.g., note that region 45 extends below gate electrode 55) the first gate electrode (see, e.g., gate electrode 55, see annotated fig. 6).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the peripheral body diode extension feature of Fukutani within the device of Nakashima in view of Fukutani further in view of Hoki, in order to achieve the expected result of expanding the peripheral body diode region around the gate electrode and increasing the current interface within the device.
Regarding claim 14, Hoki (see, e.g., figs 1-2) teaches wherein the first pillar structure (e.g., left-most p type column layer 14 + second p type column layer 14 between left-most and centered p type column layers + p type guard ring 11 adjacent to left-most p type column layer) further comprises a third pillar region (e.g., left-most p type column layer 14 between adjacent p type guard ring 11 and second p type column layer 14) between the first pillar region (e.g., left-most p type column layer 14) and the second pillar region (e.g., second p type column layer 14), and connecting (e.g., note that the third pillar region is disposed directly between the first and second pillar regions, so it electrically connects the two) an upper part of the first pillar region (e.g., left-most p type column layer 14) and an upper part of the second pillar region (e.g., second p type column layer 14).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the third pillar region of Hoki within the first pillar structure of Nakashima in view of Fukutani further in view of Hoki, in order to achieve the expected result of expanding the pillar support for the current-flow profile within the device.
Regarding claim 15, Nakashima in view of Fukutani further in view of Hoki teaches wherein the first body region (see, e.g., right-side of black division bar, see Fukutani modification done to Nakashima) and the peripheral body diode region (e.g., diode region 45d stack added via Fukutani) are spaced apart from each other (e.g., note the diode region stack doesn’t entirely overlap with the first body region, hence the two are at least slightly spaced apart), and the first body region (see, e.g., right-side of black division bar, see Fukutani modification done to Nakashima) is spaced apart (e.g., note that the first body region is placed vertically above drift layer 93, and vias/gate electrodes are disposed immediately above the drift layer 93) from a second body region (e.g., n.sup.−-type drift layer 93) that is disposed within the substrate (e.g., third metal layer 19) in the active cell region (e.g., cell region 60).
Regarding claim 16, Nakashima (see, e.g., figs. 7-8) shows wherein the active cell region (e.g., cell region 60, see green-striped region in annotated fig. 7 below) comprises a first active region (e.g., first active region of annotated fig. 7 below) including a recessed region (see, e.g., recessed geometry of cell region 60 around recess 14) and a second active region (e.g., second active region of annotated fig. 7 below), the peripheral region (e.g., source electrode 13 region) comprises a first peripheral region (e.g., source electrode 13 region left of black division bar, see annotated fig. 7) and a second peripheral region (e.g., source electrode 13 region right of black division bar, see annotated fig. 7), the first peripheral region (e.g., source electrode 13 region left of black division bar, see annotated fig. 7) comprises a first region (e.g., edge portion of source electrode 13 in recess 14 area) within the recessed region (e.g., note that source electrode 13 forms the recess 14 that recesses into the cell region 60) and a second region (e.g., portion of source electrode 13 area between recess 14 and top left corner of fig. 7) disposed between the first active region (e.g., first active region of annotated fig. 7 below) and the edge terminal region (e.g., gate electrode 16 + paragraph 28 “The portion of the gate electrode 16 exposed through the second pad opening 11B functions as an external terminal…”), the second peripheral region (e.g., source electrode 13 region right of black division bar, see annotated fig. 7 below) is disposed between the second active region (e.g., second active region of annotated fig. 7 below) and the edge terminal region (e.g., gate electrode 16 + paragraph 28 “The portion of the gate electrode 16 exposed through the second pad opening 11B functions as an external terminal…”), wherein the second region (e.g., portion of source electrode 13 area between recess 14 and top left corner of fig. 7) comprises: a first sub-region (e.g., source electrode 13 portion in top left of fig. 7, see annotated fig. 8) extending in a first direction (e.g., vertical direction of fig. 7) and disposed between the first active region (e.g., first active region of annotated fig. 3 below) and the edge terminal region (e.g., gate electrode 16 + paragraph 28 “The portion of the gate electrode 16 exposed through the second pad opening 11B functions as an external terminal…”), a second sub-region (e.g., extending source electrode 13 portion, see annotated fig. 8 below) extending in a second direction (e.g., horizontal direction) intersecting the first direction (e.g., vertical direction), and being between the first region (e.g., edge portion of source electrode 13 in recess 14 area) and the edge terminal region (e.g., gate electrode 16 + paragraph 28 “The portion of the gate electrode 16 exposed through the second pad opening 11B functions as an external terminal…”), and a third sub-region (e.g., sub-region of source electrode 13 between first sub-region and second sub-region, see annotated fig. 8 below) extending (e.g., note the third sub-region has a width extending in the horizontal direction) in the second direction (e.g., horizontal direction), and disposed between the first sub-region (e.g., source electrode 13 portion in top left of fig. 7, see annotated fig. 8) and the second sub-region (e.g., extending source electrode 13 portion, see annotated fig. 8 below) and between the first active region (e.g., first active region of annotated fig. 8 below) and the edge terminal region (e.g., gate electrode 16 + paragraph 28 “The portion of the gate electrode 16 exposed through the second pad opening 11B functions as an external terminal…”).
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Annotated Fig. 7 Annotated Fig. 8
Fukutani (see, e.g., figs. 4-5) teaches wherein the peripheral body diode region (e.g., diode region 45d stack) extends from a third sub-region (e.g., third sub-region of annotated fig. 8) of the second region to a portion of the first active region (e.g., active region 45).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the body diode region sub-region extension setup of Fukutani within the configuration of Nakashima in view of Fukutani further in view of Hoki, in order to achieve the expected result of utilizing the entire span of the sub-region for additional space for the diode stack, further improving the recovery capacity benefits within the device.
Regarding claim 17, Nakashima (see, e.g., figs. 7-8) shows wherein the first region (e.g., edge portion of source electrode 13 in recess 14 area, see annotated fig. 7 above) protrudes from the second sub-region (e.g., extending source electrode 13 portion, see annotated fig. 8 above) of the second region (e.g., portion of source electrode 13 area between recess 14 and top left corner of fig. 7).
Fukutani (see, e.g., figs. 4-5) teaches the peripheral body diode region (e.g., diode region 45d stack) extends from a third sub-region (e.g., sub-region between recess edge and corner region) to a distal end of a first region (e.g., note that the diode region 45d extends over and between the entire cell region of Fukutani, including from the recess edge to the corner regions).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the peripheral body diode extension configuration of Fukutani within the setup of Nakashima in view of Fukutani further in view of Hoki, in order to achieve the expected result of utilizing the span near the recess for additional diode space, further improving the recovery capacity benefits within the device.
Regarding claim 18, Fukutani (see, e.g., figs. 4-5) teaches wherein the peripheral body diode region (e.g., diode region 45d stack) further extends from the second peripheral region (e.g., second peripheral region, see annotated fig. 10 below) to a portion of a second active region (e.g., active cell region right of green-bar, see annotated fig. 10 below).
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Annotated Fig. 10
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the extended diode configuration of Fukutani between the second peripheral region and second active region of Nakashima in view of Fukutani further in view of Hoki, in order to achieve the expected result of providing additional diode stacks within the active region, further improving the recovery capacity benefits within the device.
Allowable Subject Matter
Claims 3 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3, the primary art of record, Nakashima (US 20240162344 A1) in view of Fukutani (US 20240072045 A1) further in view of Hoki (US 20170084693 A1) fails to teach wherein the first peripheral body diode region extends on the first pillar structure, and the second peripheral body diode region extends between the first gate electrode and the first pillar structure. These features in combination with other elements in the claim are neither disclosed nor suggested by the prior art of record.
Regarding claim 13, the primary art of record, Nakashima (US 20240162344 A1) in view of Fukutani (US 20240072045 A1) further in view of Hoki (US 20170084693 A1) fails to teach wherein the first peripheral body diode region extends on the first pillar structure, and the second peripheral body diode region extends between the first gate electrode and the first pillar structure. These features in combination with other elements in the claim are neither disclosed nor suggested by the prior art of record.
Regarding claim 19, Hoki (US 20170084693 A1) in view of Fukutani (US 20240072045 A1) teaches most aspects of the semiconductor device.
However, Hoki in view of Fukutani fails to disclose or suggest the first peripheral body diode region and the second peripheral body diode region are disposed between the first gate electrode and the first pillar structure.
Therefore, the above limitations in the entirety of the claim are neither anticipated nor
rendered obvious over the prior art of record.
Any comments considered necessary by applicant must be submitted no later than the
payment of the issue fee, and, to avoid processing delays, should preferably accompany the
issue fee. Such admissions should be clearly labeled “Comments on Statement of Reasons for
Allowance”.
Conclusion
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/THOMAS WILSON MCCOY/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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