DETAILED ACTION
This Office action responds to the application filed on 01/24/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "the secondary integrated circuit die" in lines 5-6. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 3, 4, 5, 7, 8, 9, 11, 14, 15, 16, 17, 18, 20, 21, 22, & 24 are rejected under 35 U.S.C. 103 as being unpatentable over Jee (US 20210020578) in view of Choi (US 20240079394).
Regarding Claim 1, Jee (see, e.g., fig. 4) shows an integrated circuit device comprising:
a main integrated circuit die 110 (see, e.g., para.0028) configured to communicate over a network through one or more high-speed communications interfaces (signal paths A-F, see, e.g., para.0040);
at least one secondary integrated circuit die 150 & 156 (see, e.g., para.0036), including serial interface circuitry 156 (see, e.g., para.0037),
each secondary integrated circuit die among the at least one secondary integrated circuit die being mounted on a first surface (top surface, see, e.g., annotated figure 1) of the main integrated circuit die;
Jee, however, does not explicitly disclose
the main integrated circuit die having functional circuitry
and first metallization connections extending along one or more first through-silicon vias between the functional circuitry and the serial interface circuitry of the at least one secondary integrated circuit die.
Choi (see, e.g., fig. 1) discloses a configuration wherein
the main integrated circuit die 210 (see, e.g., para.0027) having functional circuitry 211 & 213 (see, e.g., para.0027)
and first metallization connections 217 (left three connections, see, e.g., annotated figure 1, para.0034) extending along one or more first through-silicon vias (vias in which 217 are in) between the functional circuitry and the serial interface circuitry of the at least one secondary integrated circuit die 410 (see, e.g., para.0043).
Die 210 of Choi (see, e.g., para.0044) and die 110 of Jee (see, e.g., para.0028) may both be logic chips, and thus the configuration of the main integrated circuit die 210 of Choi is incorporated into the main integrated circuit die 110 of Jee. Therefore it would have been obvious one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teaching of Choi into Jee because the combination is a simple substitution of one known element for another to obtain predictable results.
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Regarding Claim 2, Jee, in view of Choi, shows the integrated circuit device of claim 1,
wherein: the first metallization connections are configured to provide data from the main integrated circuit die to the secondary integrated circuit die (through signal path C, see, e.g., para.0043);
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and the secondary integrated circuit die is configured to communicate data between the integrated circuit device and a remote integrated circuit device 150 (second 150, see, e.g., annotated figure 2, para.0044).
Regarding Claim 3, Jee, in view of Choi (see, e.g., para.0034-0035), shows the integrated circuit device of claim 1 further comprising
second metallization connections 217 (right three connections, see, e.g., annotated figure 1, para.0034) between the serial interface circuitry 156 of the at least one secondary integrated circuit die 150 and terminals 220 (see, e.g., para.0034-0035) of the main integrated circuit die.
Regarding Claim 4, Jee, in view of Choi shows the integrated circuit device of claim 3
wherein at least one metallization connection among the first metallization connections 217 (leftmost connection) extends along a respective one of the first through-silicon vias (leftmost via) between (a) elements of the functional circuitry 211 & 213 within layers of the main integrated circuit die, and (b) the first surface (top surface) of the main integrated circuit die (see, e.g., annotated figure 3).
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Regarding Claim 5, Jee, in view of Choi, shows the integrated circuit device of claim 4,
wherein: at least one metallization connection (rightmost connection) among the second metallization connections 217 extends along at least one respective second through-silicon via between (a) the first surface (top surface) of the main integrated circuit die, and (b) at least one respective terminal 220 (rightmost) of the main integrated circuit die,
the at least one respective second through-silicon via being perpendicular to the first surface of the main integrated circuit die (see, e.g., annotated figure 4).
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Regarding Claim 7, Jee, in view of Choi, shows the integrated circuit device of claim 3,
wherein at least one metallization connection (rightmost connection) among the second metallization connections 217 extends along at least one respective second through-silicon via (rightmost) between (a) the first surface (top surface) of the main integrated circuit die, and (b) at least one respective terminal 220 (rightmost) of the main integrated circuit die (see, e.g., annotated figure 4).
Regarding Claim 8, Jee, in view of Choi, shows the integrated circuit device of claim 7
wherein the respective one of the terminals 220 (rightmost) of the main integrated circuit die is on a second surface (bottom surface, see, e.g., annotated figure 4) of the main integrated circuit die opposite the first surface of the main integrated circuit di
Regarding Claim 9, Jee (see, e.g., para.0046), in view of Choi shows the integrated circuit device of claim 7,
wherein the at least one secondary integrated circuit die 150 is mounted on the first surface (top surface) of the main integrated circuit die in a contact relationship (connection between 150 to 118 which corresponds to 217 of Choi, see, e.g., para.0046) with the respective second through-silicon via (rightmost via of 217).
Regarding Claim 11, Jee, in view of Choi, shows the integrated circuit device of claim 7,
wherein: the at least one secondary integrated circuit die 150 is mounted on the first surface (top surface) of the main integrated circuit die at a distance (see, e.g., annotated figure 5) from the respective second through- silicon via (rightmost via, see, e.g., annotated figure 5);
and the at least one metallization connection among the second metallization connections includes a metallization trace (the metallization trace is considered to be the electrical current passing through metallization connection 217) from the at least one secondary integrated circuit die to the respective second through-silicon via.
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Regarding Claim 14, Jee shows a method of forming an integrated circuit device
having a main integrated circuit die 110 (see, e.g., para.0028) configured to communicate over network through one or more high-speed communications interfaces (signal paths A-F, see, e.g., para.0040), the method comprising:
mounting, on a first surface (top surface, see, e.g., annotated figure 1) of the main integrated circuit die,
at least one secondary integrated circuit die 150 & 156 (see, e.g., para.0036) including serial interface circuitry 156 (see, e.g., para.0037);
Jee, however, fails to show
the main integrated circuit die having functional circuitry
and creating first metallization connections extending along one or more first through-silicon vias between the functional circuitry and the serial interface circuitry of the at least one secondary integrated circuit die.
Choi (see, e.g., fig. 1) discloses a configuration wherein
the main integrated circuit die 210 (see, e.g., para.0027) having functional circuitry 211 & 213 (see, e.g., para.0027)
and creating first metallization connections 217 217 (left three connections, see, e.g., annotated figure 1, para.0034) extending along one or more first through-silicon vias between the functional circuitry and the serial interface circuitry of the at least one secondary integrated circuit die 410 (see, e.g., para.0043).
Die 210 of Choi (see, e.g., para.0044) and die 110 of Jee (see, e.g., para.0028) may both be logic chips, and thus the configuration of the main integrated circuit die 210 of Choi is incorporated into the main integrated circuit die 110 of Jee. Therefore it would have been obvious one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teaching of Choi into Jee because the combination is a simple substitution of one known element for another to obtain predictable results.
Regarding Claim 15, Jee, in view of Choi, shows the method according to claim 14 of forming an integrated circuit device, the method further comprising:
configuring the first metallization connections to provide data from the main integrated circuit die to the secondary integrated circuit die (through signal path C, see, e.g., para.0043);
and configuring the secondary integrated circuit die to communicate data between the integrated circuit device and a remote integrated circuit device 150 (second 150, see, e.g., annotated figure 2, para.0044).
Regarding Claim 16, Jee, in view of Choi, shows the method according to claim 14 of forming an integrated circuit device, the method further comprising
creating second metallization connections 217 (right three connections, see, e.g., annotated figure 1, para.0034) between the serial interface circuitry 156 of the at least one secondary integrated circuit die 150 and terminals 220 (see, e.g., para.0034-0035) of the main integrated circuit die.
Regarding Claim 17, Jee, in view of Choi, shows the method of forming an integrated circuit device according to claim 16,
wherein creating the first metallization connections comprises creating at least one metallization connection 217 (leftmost connection) among the first metallization connections extending along a respective of the first through- silicon vias (leftmost via) between (a) elements of the functional circuitry 211 & 213 within layers of the main integrated circuit die, and (b) the first surface (top surface) of the main integrated circuit die (see, e.g., annotated figure 3).
Regarding Claim 18, Jee, in view of Choi, shows the method of forming an integrated circuit device according to claim 17
wherein: creating the second metallization connections comprises creating at least one metallization connection among the second metallization connections 217 (rightmost connection) extending along at least one respective second through-silicon via between (a) the first surface (top surface) of the main integrated circuit die, and (b) at least one respective terminal 220 (rightmost) of the main integrated circuit die,
the at least one respective second through-silicon via being perpendicular to the first surface of the main integrated circuit die (see, e.g., annotated figure 4).
Regarding Claim 20, Jee, in view of Choi, shows the method of forming an integrated circuit device according to claim 16
wherein creating the second metallization connections comprises creating at least one metallization connection 217 among the second metallization connections (rightmost connection) extending along at least one respective second through-silicon via (rightmost via) between (a) the first surface (top surface) of the main integrated circuit die, and (b) at least one respective terminal 220 (rightmost) of the main integrated circuit die (see, e.g., annotated figure 4).
Regarding Claim 21, Jee, in view of Choi, shows the method of forming an integrated circuit device according to claim 20
wherein creating the at least one metallization connection among the second metallization connections extending along the at least one respective second through-silicon via (rightmost via) between (a) the first surface of the main integrated circuit die, and (b) at least one respective terminal (rightmost 220) of the main integrated circuit die comprises creating the at least one metallization connection 217 (rightmost connection) among the second metallization connections extending along the at least one respective second through-silicon via between (a) the first surface of the main integrated circuit die, and (b) at least one respective terminal of the main integrated circuit die on a second surface (bottom surface, see, e.g., annotated figure 4) of the main integrated circuit die opposite the first surface (top surface) of the main integrated circuit die.
Regarding Claim 22, Jee (see, e.g., para.0046), in view of Choi, shows the method of forming an integrated circuit device according to claim 20
wherein mounting, on the first surface (top surface) of the main integrated circuit die, the at least one secondary integrated circuit die including serial interface circuitry, comprises mounting the at least one secondary integrated circuit die on the first surface of the main integrated circuit die in a contact relationship (connection between 150 to 118 which corresponds to 217 of Choi, see, e.g., para.0046) with the respective second through-silicon via (rightmost via).
Regarding Claim 24, Jee, in view of Choi, shows the method of forming an integrated circuit device according to claim 20
wherein: mounting, on the first surface (top surface) of the main integrated circuit die, the at least one secondary integrated circuit die including serial interface circuitry, comprises mounting the at least one secondary integrated circuit die on the first surface of the main integrated circuit die at a distance (see, e.g., annotated figure 5) from the respective second through-silicon via; the method further comprising:
creating a metallization trace (the metallization trace is considered to be the electrical current passing through metallization connection 217) from the at least one secondary integrated circuit die to the respective second through-silicon via.
Allowable Subject Matter
Claims 6, 10, 12, 13, 19, 23, 25, & 26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached on 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO JOSE RAMOS-DIAZ/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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