DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgement is made to claim of priority to Korean Patent Application No. 10-2023-0012951 filed on January 31, 2023
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed July 13, 2026. Claim 1 is amended. Claim 4 is cancelled. The Examiner notes that claims 1-3 and 5-17 are examined.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5, 15 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang (US 2022/0278260 A1).
With respect to claim 1, Chang teaches:
A display device (abstract “display apparatus”), comprising:
a substrate (substrate 390) including a display area in which a plurality of sub-pixels ([0171] “each pixel may include a red pixel R having a red light emitting element installed therein, a green pixel G having a green light emitting element installed therein”) are disposed and a non-display area (area that includes the gate driver IC and Data driver IC at periphery of the device);
a first assembly line (311) and a second assembly line (312) disposed in the plurality of sub-pixels on the substrate (390) and spaced apart from each other;
a light emitting element (light emitting element 380) disposed on the first assembly line and the second assembly line;
and a plurality of transistors (TFTs 360 and 370) disposed in the plurality of sub-pixels,
wherein each of the plurality of sub-pixels includes a first area in which the plurality of transistors (Fig. 14 “pixel transistor region”) are disposed and a second area which is separated from the first area and in which the light emitting element is disposed (uLED region).
wherein the first assembly line (assembly wiring 311) and the second assembly line (assembly wiring 312) are connected to a low- potential power supply line (OFF voltage line Vss) to receive low-potential power (para. [0268] “gate OFF voltage line Vss 521 is connected to an assembly wiring 510.” Assembly wiring 510 is analogous to assembly lines 311 and 312 as para. [0263] teaches that the embodiment of Fig. 20 is the same as the embodiment of Fig. 13 except for Vss being connected to the assembly wiring),
wherein low-potential power is applied to each of the plurality of sub-pixels through the first assembly line and the second assembly line (para. [0271] “while the gate OFF voltage line (Vss) 521 is connected to the assembly wiring 510, all of Cp, which is a parasitic capacitance near the gate OFF voltage line (Vss) 521, has a determined value, so that the data line (Vdata) 550 may maintain an applied signal of its own.”)
With respect to claim 2, Chang further teaches:
wherein, in the first area, the first assembly line and the second assembly line are disposed to be spaced apart from each other with the plurality of transistors interposed therebetween (see Fig. 14, transistor region is between assembly wiring 311 and 312 and Fig. 12 shows at least part of SW TFT and DR TFT located between the assembly lines 311 and 312).
With respect to claim 5, Chang further teaches:
further comprising a capacitor (“metal layer 371 for a storage capacitor) disposed in each of the plurality of sub-pixels,
wherein the capacitor is disposed in the first area (capacitor Is disposed in the transistor area).
With respect to claim 15, Chang further teaches:
further comprising a high-potential power supply line disposed between the first area and the second area (VDD, which runs vertically from the uLED area to the transistor area, see Fig. 12).
With respect to claim 17, Chang further teaches:
wherein the first assembly line (311) and the second assembly line (312) are disposed to be spaced apart from the plurality of transistors (361 and 371) (see Fig. 13, assembly lines are at least vertically spaced apart from the transistors).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2022/0278260 A1) as applied to claim 1 above in view of Kim (US 2021/0265541 A1).
With respect to claim 3 Chang teaches all limitations of claim 2 upon which claim 3 depends. Chang fails to teach:
wherein the first assembly line and the second assembly line include a protrusion protruding toward the light emitting element in the second area.
Kim teaches in Fig. 17:
wherein the first assembly line (520) and the second assembly line (530) include a protrusion (protruding portions 521 and 531) protruding toward the light emitting element (350) in the second area.
Chang discloses the claimed invention except for the protrusions of the assembly lines. Kim teaches that it is known to include protrusions of the assembly. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to design the assembly lines to include protruding portions for the benefit of decreasing the distance between the electrodes where they overlap with the light emitting element while allowing the electrodes to take up less space in other portions of the device. See MPEP 2144.
Claims 6-7, 9-11, 13-14, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2022/0278260 A1) as applied to independent claim 1 above and further in view of Son (US 2022/0285427 A1).
With respect to claim 6, Chang teaches all limitations of claim 1 upon which claim 6 depends, Chang fails to teach in combination:
wherein the plurality of transistors include a first transistor, a second transistor, and a third transistor,
and wherein the capacitor is disposed between the second transistor and the first transistor in a plan view and is disposed between the second transistor and the third transistor in a plan view.
Son teaches in Figs. 2 and 9:
wherein the plurality of transistors includes a first transistor (second transistor M2), a second transistor (first transistor M1), and a third transistor (third transistor M3),
and wherein the capacitor (capacitor Cst) is disposed between the second transistor (M1) and the first transistor (M2) in a plan view and is disposed between the second transistor (M1) and the third transistor (M3) in a plan view (see Fig. 9).
Chang discloses the claimed invention except for the number and layout of the transistors and capacitors. Son teaches that it is known to design a transistor and capacitor circuit with the layout and interconnections described in claims 6 and 7 set forth in Figs. 2 and 7. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention modify Chang with the transistor and capacitor circuit of Son for the purpose of controlling a light emitting element of a sub pixel. See MPEP 2144.
With respect to claim 7, Son further teaches in Fig. 2:
further comprising a reference line (sensing line SENL connected to a reference power source),
a data line (data line DL),
a scan line (scan line SL),
and a high-potential power supply line (first power source VDD) connected to the plurality of sub-pixels (sub pixel SPX),
wherein a source electrode of the first transistor (M2) is connected to a gate electrode of the second transistor (M1) (connected at node N1),
a drain electrode of the first transistor (M2) is connected to the data line (DL), and a gate electrode of the first transistor (M1) is connected to the scan line (SL),
wherein a source electrode of the second transistor (M1) is connected to the light emitting element (para. 81 “a first electrode (e.g., a source electrode) of the first transistor M1 and the first electrode ELT1 (e.g., an anode electrode) of the light emitting unit EMU are connected to each other.”),
a gate electrode of the second transistor (M1) is connected to the source electrode of the first transistor (M2),
and a drain electrode of the second transistor (M1) is connected to the high-potential power supply line (VDD),
and wherein a source electrode of the third transistor (M3) is connected to the source electrode of the second transistor (M1, connected through N2), a gate electrode of the third transistor (M3) is connected to the scan line (SL),
and a drain electrode of the third transistor (M3) is connected to the reference line (SENL).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Chang in view of Son as explained above.
With respect to claim 9, Chang and Son further teaches in Fig. 8 of Son:
a plurality of inorganic layers (insulating layers INS1, INS2, INS3, INS4, and INS5 of Son) disposed in the first area (area with light emitting elements) and the second area (area with transistors, which is a separated from the area with light emitting elements in Chang) and having a first opening (see annotated Fig. 8 below) disposed therein and overlapping the light emitting element;
and a reflective layer (the reflective layer of first and second electrodes ELT1 and ELT2 which may include at least one reflective electrode layer) disposed on the plurality of inorganic layers (disposed on INS5) and disposed to overlap the light emitting element (light emitting elements LD) in the first opening.
The device of Chang/Son is a base device upon which the claimed invention can be seen as an improvement. The layout of the light emitting element and inorganic layers as described above is a known technique as taught by Son that could be applied to the device of Chang/Son. One of ordinary skill in the art would have recognized that applying the known technique would have yielded predictable results of a working pixel structure for a display that improves on the device of Chang/Son by providing a reflection layer and bank to better control light emission.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further incorporate the teachings of Son into the device of Chang/Son to use the light emitting element layout of Son. The ordinary artisan would have been motivated to modify Chang/Son in the manner set forth above to improve the light emission properties of Chang/Son.
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With respect to claim 10, Son further teaches:
a first passivation layer (sixth insulating layer INS6) disposed on the plurality of inorganic layers (insulating layers INS1-INS5) and the reflective layer (reflective portion of ELT1 and ELT2);
a planarization layer (bank BNK) disposed on the first passivation layer (INS6) and having a second opening (see annotated Fig. 8 above) disposed therein and overlapping the light emitting element (LD);
and a second passivation layer (INS7) disposed on the planarization layer (BNK) and the first passivation layer (INS6) and in contact with the first passivation layer in the second opening (INS7 is in indirect physical contact with INS6 through BNK and CCL).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Chang in view of Son as explained above.
With respect to claim 11, Chang teaches that the assembly lines are located directly below the light emitting element. Modifying Chang by Son to include first and second openings that the light emitting element is disposed in teaches:
wherein the first assembly line (311 of Chang) and the second assembly line (312 of Chang) are disposed on the second passivation layer (on bottom side of INS6 of Son) and are disposed in the first opening and the second opening (see annotated Fig. 8 of Son above, assembly lines of Chang are below the light emitting element which is analogous to LD of Son).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Chang in view of Son as explained above.
With respect to claim 13, Son further teaches:
wherein an upper surface of the planarization layer (BNK) is disposed at a position higher than an upper surface of the light emitting element (LD).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Chang in view of Son as explained above.
With respect to claim 14, Son does not specify the material of the reflective layer and source and drain electrodes relied upon for the rejection of claim 9 above.
However, para. 212 of Son teaches that each of the conductive patterns, electrodes, and/or lines may be made from “one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu)”
Therefore, it would be obvious to choose materials from the above list to meet the limitation:
wherein the reflective layer (reflective electrode layer of ELT1) is formed of a same material as source electrodes or drain electrodes (SE or DE) of the plurality of transistors.
With respect to claim 16, Son further teaches:
wherein the reflective layer (reflective portion of ELT1 and ELT2) is disposed to cover a bottom and a side portion of the first opening (covers the side portion and partially covers the bottom portion of first opening as defined in annotated Fig. 8 above) so as to reflect light emitted from the light emitting element to a front direction of the display device.
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Chang in view of Son as explained above.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2022/0278260 A1) and Son (US 2022/0285427 A1) as applied to claim 6 above and further in view of Koo (US 2018/0175077 A1) and Lee (US 2020/0219770 A1).
With respect to claim 8, Chang/Son teaches all limitations of claim 6 upon which claim 8 depends. Chang/Song fails to teach:
further comprising a light blocking layer disposed below the plurality of transistors,
wherein the capacitor includes a first capacitor electrode,
a second capacitor electrode disposed on the first capacitor electrode,
and a third capacitor electrode disposed on the second capacitor electrode, wherein the first capacitor electrode is connected to the light blocking layer,
wherein the second capacitor electrode is formed of a same material as a gate electrode of the second transistor,
and wherein the third capacitor electrode is connected to a source electrode or a drain electrode of the second transistor.
With respect to claim 8, Koo teaches:
further comprising a light blocking layer (light shielding layer LS) disposed below the plurality of transistors (disposed at least below Tdr, including active layer 140, of the plurality of transistors),
wherein the capacitor includes a first capacitor electrode (right portion of LS acts as an electrode for Cst 1, see Fig. 4),
wherein the first capacitor electrode is connected to the light blocking layer (first capacitor electrode is the rightmost portion of light shielding layer LS),
Chang/Son discloses the claimed invention except light blocking layer that is part of the capacitor. Koo teaches that it is known to make a storage capacitor in which one electrode is connected to the light blocking layer. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang/Son with light blocking layer that acts as a capacitor electrode of Koo for the purpose of increasing the area of the storage capacitor ([0145] of Koo). See MPEP 2144.
Lee teaches:
wherein the capacitor includes a second capacitor electrode (second capacitor electrode 136) disposed on the first capacitor electrode (first capacitor electrode 116),
and a third capacitor electrode (third capacitor electrode 156) disposed on the second capacitor electrode,
wherein the second capacitor electrode (136) is formed of a same material (para. 69 “The gate electrode 132, the connection pattern 134, the second capacitor electrode 136, and the gate line may be formed of at least one of aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), nickel (Ni), tungsten (W), and an alloy thereof.”) as a gate electrode (gate electrode 132) of the second transistor,
and wherein the third capacitor electrode (156) is connected to a source electrode or a drain electrode (source and drain electrodes 152 and 154, 156 is connected to 154, see Fig. 3A) of the second transistor.
Chang/Son/Koo discloses the claimed invention except for the structure of the capacitor electrodes and their connections to the light blocking layer and transistors. Lee teaches that it is known to make a storage capacitor in which one electrode is connected to the light blocking layer, one is connected to a source electrode or drain electrode of a second transistor, and one electrode is made from a same material as the gate electrode of the second capacitor. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim/Koo/Son with the capacitor structure of Lee for the purpose of improving integration of the circuit structure. See MPEP 2144.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2022/0278260 A1) and Son (US 2022/0285427 A1) as applied to claim 11 above and further in view of Choi (US 2022/0165756 A1).
With respect to claim 12, Chang/Son teaches all limitations of claim 11 upon which claim 12 depends. Chang does not teach:
wherein portions of the first assembly line and the second assembly line disposed in the first opening and the second opening are formed of a transparent conductive material.
Choi teaches:
wherein the first assembly line and the second assembly line are formed of a transparent conductive material ([0130] “The assembly electrodes 1011 and 1012 may be implemented as transparent electrodes (ITO)”).
It would have been obvious to modify Chang/Son with the teaching of Choi to make the assembly lines out of a transparent material to mee the limitation “wherein portions of the first assembly line and the second assembly line disposed in the first opening and the second opening are formed of a transparent conductive material” for the purpose of allowing to transmit through the device and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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