Attorney’s Docket Number: 18421986
Filing Date: 01/25/2024
Claimed Priority Date: 07/27/2021 (PCT CN2021/108744)
Applicants: Jing et al
Examiner: Aneesa Baig
DETAILED ACTION
This Office action responds to the election filed on 06/01/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s species elections with traverse in the reply filed on 06/01/2026, is acknowledged.
With regards to the species restriction, examiner agrees with the applicants reasoning, leaving the species restriction withdrawn.
Accordingly, claims 1-20 are pending in this application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1- 16,19,20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention.
Claim 1 recites “” at L. 5-7, then later recites “plurality of ferroelectric capacitors are arranged in a first direction perpendicular to the substrate.” It is unclear what part of the surface the first direction is perpendicular to, thus rendering the claim indefinite. For the purpose of examination, the claim will be construed as reciting -- plurality of ferroelectric capacitors are arranged in a first direction perpendicular to the surface of the substrate --, as best understood by the examiner in view of the original disclosure, until further clarifications are provided by the applicant.
Claims 2-16 depend on Claim 1, thus inherit the deficiencies identified supra.
Claim 2 is similarly understood to be the following -- plate line layer is located on a first plane parallel to the surface of the substrate --.
Regarding Claim 10, there is lack of antecedent basis for the terms “the surface opposite to the second electrode in the first electrode”, “the first wall surface, “the surface opposite to the first electrode in the second electrode,” “the second wall surface” deeming the claim indefinite. Examiner understands these terms to have an “a” replacing the “the,” until further clarifications are provided by the applicant.
Regarding Claim 14, there is lack of antecedent basis for the term “the periphery of the semiconductor layer” and “the semiconductor layer” as the preceding claim 1 or 13 lacks mention of these terms, deeming the claim indefinite. Examiner understands claim 14 was to depend from the chain of Claim 4, as best understood by the examiner in view of the original disclosure, until further clarifications are provided by the applicant.
Regarding Claim 15, there is lack of antecedent basis for the terms “the gate of the transistor”, “the first electrode of the transistor,” “the second electrode of the transistor,” as the preceding claim 1 lacks mention of these terms, deeming the claim indefinite. The examiner is understanding claim 15 was to depend from Claim 4, as best understood by the examiner in view of the original disclosure, until further clarifications are provided by the applicant.
Claim 16 depends on Claim 15, thus inherit the deficiencies identified supra.
Regarding Claim 19, the claim recites “the first word line electrical control signal” and “the selected ferroelectric capacitor.” These terms lack antecedent basis and hence are indefinite. For the purpose of examination, the claim will be construed as reciting -- a first word line electrical control signal and a selected ferroelectric capacitor, as best understood by the examiner in view of the original disclosure, until further clarifications are provided by the applicant. Further, claim 19 recites “the selected ferroelectric capacitor”. There is lack of antecedent basis for this term, as Claim 1 does not mention this term and it is unclear if the selected transistor is the same as Claim 18. Examiner assumes the selected capacitor is the same as claim 18, unless further amendments are provided by applicant. The dependency of claim 19 must updated or amendments must be provided accordingly to overcome this rejection.
Regarding Claim 20, the claim is understood as -- plurality of ferroelectric capacitors are arranged in a first direction perpendicular to the surface of the substrate --, as best understood by the examiner in view of the original disclosure, until further clarifications are provided by the applicant.
Note: As identified above, multiple claims contain inconsistencies in identifying features, thus raising several clarity and antecedent basis issues. Applicant is encouraged to review all claims for consistency in response to this Office action.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 12, 20 are rejected under 35 U.S.C. 102 (a)(1) as anticipated by Lu et al (US 10403631 B1, Hereinafter Lu).
Regarding Claim 1, Lu (e.g., Figure 2 in reference to Figure 1B, page 30 Col 12-20]) shows all aspects of the instant invention, including, a ferroelectric memory device comprising:
a substrate (206); and
a plurality of memory cells (e.g., Fig 2 shows two memory cells), formed on the substrate, wherein each memory cell comprises a transistor (220) and a plurality of ferroelectric capacitors (204-1 and 204-2);
the transistor and the plurality of ferroelectric capacitors are arranged in a first direction perpendicular to surface of the substrate;
each of the plurality of ferroelectric capacitor comprises a first electrode layer (222), a second electrode layer (226-1), and a ferroelectric layer formed between the first electrode layer and the second electrode layer (224-1);
the first electrode layers of every two adjacent ferroelectric capacitors of the plurality of ferroelectric capacitors are in contact, to form a shared first electrode layer that extends in the first direction (both first electrodes are continuous and run in the center to both capacitors); and
the shared first electrode layer is electrically connected to the transistor (Fig 2)
Regarding Claim 2, Lu shows wherein the ferroelectric memory further comprises
a plate line layer (214 and 215), wherein the plate line layer is located on a first plane parallel to the surface of the substrate; and
the plurality of second electrode layers of the plurality of ferroelectric capacitors located on the first plane are interconnected through the plate line layer (Electrodes 226-1 and 226-2 are electrically connected to 214 and 215, respectively).
Regarding Claim 3, Lu shows the capacitors are formed through a BEOL process (Fig 1B and Col 8 “Peripheral interconnect layer 404 can include interconnects, such as interconnect lines and via contacts of MEOL and/or BEOL”).
Regarding Claim 12, Lu shows the transistor may be formed in a GAA process ( Col 15 “Channel structure 228, gate dielectric layer 230, and gate conductor 232 can be disposed radially from the center”)
Regarding Claim 20, see comments from Claim 1, as they would be considered repeated here.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-8, 10,15,17 are rejected under 35 U.S.C. 103 as being unpatentable over Lu.
Regarding Claim 4, Lu shows in (Fig 2, with reference to Fig 1B)
wherein the transistor (220, Col 14) comprises a gate (232), a semiconductor layer (228), a first electrode (Fig 1B bit line contacts 136), a second electrode (upper portion of first upper electrode 222-2), and a gate dielectric layer (230),
wherein the first electrode and the second electrode are arranged in the first direction, the gate is a vertical structure that extends in the first direction, one of two opposite sides of the gate in a second direction has the semiconductor layer (See Figures), the semiconductor layer is electrically connected to the first electrode and the second electrode (“channel structure 228 can be disposed above and electrically connected to the continuous electrode including first electrodes 222-2 and 222-1 by its source/drain region at the lower portion.), the gate and the semiconductor layer are isolated by the gate dielectric layer, and the second direction is a direction parallel to the substrate.
While Lu does not disclose second electrode as a separately labeled item, note that a limitation in a claim with respect to a material property in a claimed device does not differentiate the claimed device from prior-art device if the prior-art device teaches all the structural limitations in the claims.
In the instant application the second electrode 52 and the first electrode layer 61 are comprised of the same materials ([0127] and [0133] “TiN (titanium nitride), Ti (titanium), Au (aurum), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (cuprum), Ru (ruthenium), and Ag (argentum)”). Hence, may be a continuous electrode. Since the electrodes are at least comprised of same materials as each other in the instant application, both layers are capable of forming the same function. Similarly in Lu, the upper portion of first upper electrode 222-2 is comprised of the same materials as the electrode of the upper capacitor, hence it teaches all the structural limitations in the claims due to the same material property of the electrode.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the upper portion of first upper capacitor electrode perform the function of the second electrode of the transistor, due to the same material properties.
Regarding Claim 5, Lu shows the device is a vertical structure extending in the first direction.
Regarding Claim 6, Lu shows the semiconductor layer is between the first and second electrode (Fig 2, in reference to fig 1B)
Regarding Claim 7, See comments from Claims 4-6, as they would be considered repeated here.
Regarding Claim 8, See comments from Claims 4-6, as they would be considered repeated here.
Regarding Claim 10, Lu shows the gate (232) is located in a region between the first electrode and the second electrode (a first electrode (Fig 1B bit line contacts 136), a second electrode (upper portion of first upper electrode 222-2).
Regarding Claim 15, Lu shows the ferroelectric memory further comprises the following:
a bit line (bit lines 138), a word line ((“Gate conductor 232 can extend laterally and function as a gate line of transistor 220 as well as a word line of ferroelectric memory cell”); and a plate line (a plate line layer (214 and 215),),
wherein the gate of the transistor is electrically connected to the word line (See above)
the first electrode of the transistor is electrically connected to the bit line (Bit line connected to first electrode (Fig 1B bit line contacts 136),);
the second electrode of the transistor (second electrode upper portion of first upper electrode 222-2),) is electrically connected to the shared first electrode layer; and
the second electrode layer of the ferroelectric capacitor is electrically connected to the plate line (Fig 2 in reference to Fig 1B).
Regarding Claim 17, Please see comments from Claims 4 and 15, as they would be considered repeated here.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lu in view of Chen et al (US 20210020747 A1, hereinafter Chen).
Regarding Claim 13, while Lu shows a transistor formed by GAA process, it is silent regarding a transistor formed through a CAA process.
Chen (e.g., Fig 1-3, 23, 25 [0001]-[0050], [0133]), on the other hand and in a related field of semiconductor devices, teaches using a CAA transistor process in devices with multiple transistors stacked together. Chen teaches that in a GAA process, field-effect thereof is contributed by a single gate, and when multiple GAA field-effect transistors are electrically connected in parallel or arranged side-by-side in structure, a potential of any point in the channel is still contributed by a single gate. In CAA, due to channel carriers of the FET are not confined by the single gate structures, there are multiple current path (from the drain to the source regions) formed by the extra degree of freedom in 3D space.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have a transistor formed through a CAA process in the device of Lu, as taught by Chen, as forming the channel outside the gate of the channel all-around semiconductor device, the channel is not confined in a single gate structure, but has multiple current paths in a three-dimensional space. Hence, If the circuit structure is applied to the field effect transistor, an output current per unit area may be greatly increased at a same sub-threshold swing, and the device density may be further increased.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Lu in view of Pan et al (US 20200051607 A1, hereinafter Pan).
Regarding Claim 18, while Lu shows the ferroelectric memory structure of Claim 1, it does not detail operation of the device in a write stage. However, note that a limitation in a claim with respect to the manner in which a claimed device is intended to be used does not differentiate the claimed device from a prior-art device if the prior-art device teaches all structural limitations in the claims and the functional limitations are found to be inherent in the prior-art device. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See Hewlett-Packard Co. v. Bausch & Lomb Inc. and the related case law cited therein which makes it clear that it is the final product per se which must be determined in a device claim, and not the patentability of its functions (909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990)). As stated in Best,
Where the claimed and prior art products are identical or substantially identical in structure or composition, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
Note that the applicant has burden of proof once the examiner establishes a sound basis for believing that the products of the applicant and the prior art are the same. See In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990).
Pan (Fig 1B, 2, 9, 12A 12B, [0145]-[0170]), on the other hand and in a related field and similar 1T-nC ferroelectric memory device structure, teaches applying a word line signal to the WL to turn on the transistor, a bit line control signal to the bit line, and a plate line signal to the plate line to polarize respective ferroelectric memory cells.
Further, Pan teaches the plate line time sequence can be determined by various factors, including the type of operations (e.g., read or write), the arrangement of ferroelectric memory cells (e.g., whether all bit lines are accessed at once for the selected word line), the valid states of data that can be written into capacitors.
In the instant case, Lu in view of Pan teaches all structural aspects of the semiconductor device according to the claimed invention, and Pan teaches that time sequences are determined by the arrangement of cells. Furthermore, the structure of Lu in view of Pan is capable of performing the claimed function due to the arrangement and structure of the device cells.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANEESA RIAZ BAIG whose telephone number is (571)272-0249. The examiner can normally be reached Monday-Friday 8am-5pm EST.
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/ANEESA RIAZ BAIG/
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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