DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species III in the reply filed on 06/19/2026 is acknowledged. The traversal is on the ground(s) that there is no serious search burden in examining all claims/species in the application. This is not found persuasive because each species has at least one mutually exclusive feature different from all other species and it is assumed that none are obvious variants of one another. Accordingly, the species or groupings of patentably indistinct species require a different field of search (e.g., searching different classes /subclasses or electronic resources, or employing different search strategies or search queries).
The requirement is still deemed proper and is therefore made FINAL.
Claims 4, 7, 10-11 and 18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 06/19/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation "the second conductive plate". There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 12-13, 15-17 and 20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Do et al. (US-20240222963-A1 – hereinafter Do).
Regarding claim 1, Do teaches an electrostatic discharge protection device (Fig.2 20; ¶0041), comprising:
a P-type semiconductor substrate (Fig.2 SUB; ¶0041);
an N-type well region (Fig.2 NW; ¶0041) located in the P-type semiconductor substrate (SUB);
a first N-type doped region (Fig.2 n1; ¶0041) located on the N-type well region (NW);
a P-type well region (Fig.2 PW; ¶0041) located in the P-type semiconductor substrate (SUB) and adjacent to the N-type well region (NW);
a second N-type doped region (Fig.2 n2; ¶0041) located on the P-type well region (PW), wherein the first N-type doped region (n1) is spaced apart from the second N-type doped region (n2) by an isolation feature (an isolation portion between n1 and n2 is depicted but not labeled);
a first P-type doped region (Fig.2 p3; ¶0041) located on the P-type well region (PW), wherein the first P-type doped region (p3) and the second N-type doped region (n2) are spaced apart from each other; and
a first conductive plate (Fig.2 M12; ¶0042) disposed overlapping the isolation feature (unlabeled);
wherein the first N-type doped region (n1) and the first conductive plate (M12) are electrically connected to a power-supply terminal (Fig.1 VDD; ¶0030), and
wherein the second N-type doped region (n2) and the first P-type doped region (p3) are electrically connected to a ground terminal (Fig.1 VSS; ¶0030).
Regarding claim 3, Do teaches the electrostatic discharge protection device as claimed in claim 2, wherein the first projection of the first conductive plate (M12) is separated from the second N-type doped region (n2).
Regarding claim 12, Do teaches the electrostatic discharge protection device, as claimed in claim 1, further comprising:
a first fin (n1 is a first fin), a second fin (n2 is a second fin) and a third fin (p3 is a third fin) protruding from the P-type semiconductor substrate (SUB) and parallel to one another, wherein the first fin (n1 is a first fin) and the second fin (n2 is a second fin) are located on opposite sides of the isolation feature (unlabeled), and
wherein the first N-type doped region (n1) is located in the first fin (n1 is a first fin), the second N-type doped region (n2) is located in the second fin (n2 is a second fin), and the first P-type doped region (p3) is located in the third fin (p3 is a third fin).
Regarding claim 13, Do teaches the electrostatic discharge protection device as claimed in claim 1, wherein:
the first N-type doped region (n1), the P-type well region (PW) and the second N-type doped region (n2) form a parasitic bipolar junction transistor (Fig.2 Qp/n; ¶0039),
wherein a base (PW) and an emitter (n2) of the parasitic bipolar junction transistor (Qp/n) is electrically connected to the ground terminal (VSS), and
wherein a collector (n1) of the parasitic bipolar junction transistor (Qp/n) is electrically connected to the power-supply terminal (VDD).
Regarding claim 15, Do teaches an electrostatic discharge protection device (Fig.2 20; ¶0041), comprising:
a P-type semiconductor substrate (Fig.2 SUB; ¶0041); and
an N-type field oxide field-effect transistor (all other claimed components are taught by Do, so this limitation is met) formed on the P-type semiconductor substrate (SUB), wherein the field oxide field-effect transistor comprises:
an N-type well region (Fig.2 NW; ¶0041) and a P-type well region (Fig.2 PW; ¶0041) located in the P-type semiconductor substrate (SUB) and adjacent to each other;
a first N-type source/drain doped region (Fig.2 n1; ¶0041) located on the N-type well region (NW);
a second N-type source/drain doped region (Fig.2 n2; ¶0041) located on the P-type well region (PW);
an isolation feature (an isolation portion between n1 and n2 is depicted but not labeled) located in the P-type semiconductor substrate (SUB) and between the first N-type source/drain doped region (n1) and the second N-type source/drain doped region (n2);
a gate electrode (Fig.2 Gate; ¶0039) comprising a first conductive plate (Fig.2 M12; ¶0042) disposed directly above the isolation feature (unlabeled) and the P-type well region (PW); and
a P-type bulk doped region (Fig.2 p3; ¶0041) located on the P-type well region (PW) and spaced apart from the second N-type source/drain doped region (n2);
wherein the first N-type source/drain doped region (n1) is electrically connected to the gate electrode (Gate), and
wherein the second N-type source/drain doped region (n2) is electrically connected to the P-type bulk doped region (p3).
Regarding claim 16, Do teaches the electrostatic discharge protection device as claimed in claim 15, further comprising:
a first fin (n1 is a first fin), a second fin (n2 is a second fin) and a third fin (p3 is a third fin) protruding from the P-type semiconductor substrate (SUB) and parallel to one another,
wherein the first N-type source/drain doped region (n1) is located in the first fin (n1 is a first fin), the second N-type source/drain doped region (n2) is located in the second fin (n2 is a second fin), and the first P-type bulk doped region (p3) is located in the third fin (p3 is a third fin).
Regarding claim 17, Do teaches the electrostatic discharge protection device as claimed in claim 15, wherein the first conductive plate (M12) is electrically connected to a power-supply terminal (Fig.1 VDD; ¶0030), and the P-type bulk doped region (p3) is electrically connected to a ground terminal (Fig.1 VSS; ¶0030).
Regarding claim 20, Do teaches the electrostatic discharge protection device as claimed in claim 15, wherein:
the first N-type source/drain doped region (n1), the P-type well region (PW) and the second N-type source/drain doped region (n2) form a parasitic bipolar junction transistor (Fig.2 Qp/n; ¶0039),
wherein a base (PW) and an emitter (n2) of the parasitic bipolar junction transistor (Qp/n) is electrically connected to a ground terminal (VSS), and
wherein a collector (n1) of the parasitic bipolar junction transistor (Qp/n) is electrically connected to a power-supply terminal (VDD).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, 5-6, 8-9 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Do in view of Xu (US-20230017089-A1).
Regarding claim 2, Do teaches the electrostatic discharge protection device as claimed in claim 1, wherein a first projection of the first conductive plate (M12) is directly above the P-type well region (PW).
Do does not teach wherein a first projection of the first conductive plate on a top surface of the isolation feature is completely located within the isolation feature directly above the P-type well region.
Xu teaches an electrostatic discharge (ESD) protection device (Fig.2 of Xu) comprising a conductive plate (Fig.2 160; ¶0022 of Xu) that is completely located within an isolation feature (oxide layer; ¶0022 of Xu) directly above a P well (Fig.2 210; ¶0020 of Xu) and not above a P or N type doped region (Fig.2 of Xu).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, for the conductive plate of Do (M12 of Do) to be located within the isolation feature (unlabeled in Fig.2 of Do) and not above a doped region as taught by Xu (160 of Xu) to arrive at the claimed invention. This modification is obvious because it is a matter of design choice where all other claimed components are required by Fig.2 of both Do and Xu.
Regarding claim 5, the aforementioned combination of Do in view of Xu from claim 2 teaches the electrostatic discharge protection device as claimed in claim 2.
The aforementioned combination does not teach the ESD protection device further comprising:
a second conductive plate disposed overlapping the isolation feature, wherein the second conductive plate is electrically connected to the power supply terminal.
Xu teaches a second conductive plate (Fig.2 160 right; ¶0022 of Xu) that is completely located within a second isolation feature (oxide layer; ¶0022 of Xu) directly above a P well (210 of Xu) and not above a P or N type doped region (Fig.2 of Xu) and electrically connected to a power supply.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include a second conductive plate (160 right of Xu) that is identical to the original conductive plate of Do (M12 of Do) to arrive at the claimed invention. A practitioner would have been motivated to make this modification for the benefit of facilitating a second ESD protection diode.
Regarding claim 6, Do in view of Xu teaches the electrostatic discharge protection device as claimed in claim 1, wherein the first conductive plate (M12 of Do) and the second conductive plate (160 right of Xu) are located at the same level (see Fig.2 of Xu). It is believed this claim is supposed to depend from claim 5 instead of claim 1, so the claim 5 combination is being referenced.
Regarding claim 8, the aforementioned combination of Do in view of Xu from claim 5 teaches the electrostatic discharge protection device as claimed in claim 5, wherein a second projection of the second conductive plate (160 right of Xu) on the top surface of the isolation feature (unlabeled in Fig.2 of Do) is completely located within the isolation feature.
Regarding claim 9, the aforementioned combination of Do in view of Xu from claim 8 teaches the electrostatic discharge protection device as claimed in claim 8, wherein the first projection (projection of M12 of Do) is separated from the second projection (projection of 160 right of Xu).
Regarding claim 19, Do teaches the electrostatic discharge protection device as claimed in claim 15.
Do does not teach wherein the gate electrode further comprises:
a second conductive plate disposed overlapping the isolation feature, wherein the second conductive plate is electrically connected to a power-supply terminal.
Xu teaches a second conductive plate (Fig.2 160 right; ¶0022 of Xu) that is completely located within a second isolation feature (oxide layer; ¶0022 of Xu) directly above a P well (210 of Xu) and not above a P or N type doped region (Fig.2 of Xu) and electrically connected to a power supply.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include a second conductive plate (160 right of Xu) that is identical to the original conductive plate of Do (M12 of Do) to arrive at the claimed invention. A practitioner would have been motivated to make this modification for the benefit of facilitating a second ESD protection diode.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Do in view of Yuki et al. (US-20240290778-A1).
Regarding claim 14, Do teaches the electrostatic discharge protection device as claimed in claim 1.
Do does not teach wherein the first conductive plate is separated from the isolation feature by a dielectric layer.
Yuki teaches an ESD protection device comprising a dielectric layer (Fig.7 80; ¶0111 of Yuki) above an isolation feature (Fig.7 70; ¶0111 of Yuki) wherein the dielectric layer surrounds the components above the isolation feature.
It would be obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the dielectric layer of Yuki (80 of Yuki) directly above the isolation feature of Do (unlabeled portion of Fig.2 of Do) to arrive at the claimed invention. A practitioner would have been motivated to make this modification to electrically insulate and avoid short circuiting between the components above the isolation feature.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. (US-12336301-B2 and US-20240222959-A1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THADDEUS J KOLB whose telephone number is (571)272-0276. The examiner can normally be reached Monday - Friday, 8:30am - 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/T.J.K./ Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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