Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
1. Applicant's election, with traverse, of claims 1-12 in the “Response to Restriction Requirement” filed on 05/04/2026 is acknowledged and entered by the Examiner.
Applicant’s arguments, in “Applicant Arguments/Remarks Made” with the reply “Response to Election / Restriction Filed” filed on 05/04/2026”, see “Because the method claims include process steps for "forming" a product with the structural limitations recited in Claim 1, including the non-parallel metal layer planes and the conductive paths between various combinations of substrate, first die, and second die, the Office has not shown that the product of Claim 1 can be made by a materially different process than the process in Claim 13” (remarks on page 2) have been fully considered.
The examiner has found the Applicant’s arguments to be persuasive. Therefore, the restriction requirement as set forth in the Office action mailed on 03/25/2026 is hereby withdrawn.
In view of the above noted withdrawal of the restriction requirement, applicant is advised that if any claim presented in a combination or divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application.
Once a restriction requirement is withdrawn, the provisions of 35 U.S.C. 121 are no longer applicable. See In re Ziegler, 443 F.2d 122, 1215, 170 USPQ 129, 131-32 (CCPA 1971). See also MPEP § 804.01.
This office action consider claims 1-20 pending for prosecution.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (100; Fig 3A; [0063]) = (element 100; Figure No. 3A; Paragraph No. [0063]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
2. Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al. (US 20220320047 A1; hereinafter Chang).
Regarding claim 1, Chang teaches a device (see the entire document, specifically Fig. 1+; [0006+], and as cited below), comprising:
a first die (501; see Figs. 7A-7D; [0061]) physically and electrically connected to a first set of redistribution layers (375; see Figs. 7A-7D; [0062-0063]), the first set of redistribution layers (375; see Figs. 7A-7D; [0062-0063, 0069-0070]) including a first set of metal layers (see Figs. 7A-7D; [0062-0063, 0069-0070]) oriented along a first plane; a substrate (499; see Figs. 7A-7D; [0071]); and a second die (502; see Figs. 7A-7D; [0066-0069]) disposed between the first set of redistribution layers (375; see Figs. 7A-7D; [0062-0063]) and the substrate (499; see Figs. 7A-7D; [0071]) and physically and electrically connected to a second set of redistribution layers ({314, 502b}; see Figs.7B, 9; see [0067, 0073]; see [007], where it says “Junction circuit 375-3 may include a bonding via 375c connected to a second contact 502b-6 (e.g., combination copper trench/via), a bonding pad 375a formed over a metal-free area 650b (e.g., silicon area) of a second interface surface, and a bonding trench 375b that connects the bonding via 375c to the bonding pad 375a”; thus, it is construed that layers ({314, 502b} is redistribution layers), the second set of redistribution layers ({314, 502b}; see Figs.7B, 9; see [0067, 0073]; see [007], where it says “Junction circuit 375-3 may include a bonding via 375c connected to a second contact 502b-6 (e.g., combination copper trench/via), a bonding pad 375a formed over a metal-free area 650b (e.g., silicon area) of a second interface surface, and a bonding trench 375b that connects the bonding via 375c to the bonding pad 375a”; thus, it is construed that layers ({314, 502b} is redistribution layers) including a second set of metal layers ({314, 502b}; see Figs.7B, 9; see [0067, 0073]; see [007], where it says “Junction circuit 375-3 may include a bonding via 375c connected to a second contact 502b-6 (e.g., combination copper trench/via), a bonding pad 375a formed over a metal-free area 650b (e.g., silicon area) of a second interface surface, and a bonding trench 375b that connects the bonding via 375c to the bonding pad 375a”; thus, it is construed that layers ({314, 502b} is redistribution layers) oriented along a second plane (see Figs. 7A-7D; see [0065-0070]), wherein the second plane is non-parallel with respect to the first plane (see Figs. 7A-7D; see [0065-0070]), and wherein the second set of metal layers ({314, 502b}; see Figs.7B, 9; see [0067, 0073]; see [007], where it says “Junction circuit 375-3 may include a bonding via 375c connected to a second contact 502b-6 (e.g., combination copper trench/via), a bonding pad 375a formed over a metal-free area 650b (e.g., silicon area) of a second interface surface, and a bonding trench 375b that connects the bonding via 375c to the bonding pad 375a”; thus, it is construed that layers ({314, 502b} is redistribution layers) define conductive paths between various combinations of the substrate (499; see Figs. 7A-7D; [0071]), the first die (501; see Figs. 7A-7D; [0061]), and the second die (502; see Figs. 7A-7D; [0066-0069]).
Regarding claim 2, Chang teaches all of the features of claim 1.
Chang further teaches wherein the second plane is orthogonal to the first plane (see Figs. 7A-7D; see [0065-0071]).
Regarding claim 3, Chang teaches all of the features of claim 1.
Chang further teaches wherein at least one metal trace of the second set of metal layers ({314, 502b}; see Figs.7B 7D, 9; see [0067, 0073]; see [007], where it says “Junction circuit 375-3 may include a bonding via 375c connected to a second contact 502b-6 (e.g., combination copper trench/via), a bonding pad 375a formed over a metal-free area 650b (e.g., silicon area) of a second interface surface, and a bonding trench 375b that connects the bonding via 375c to the bonding pad 375a”; thus, it is construed that layers ({314, 502b} is redistribution layers) is electrically connected at a first end to a contact of the first set of redistribution layers (375; see Figs. 7A-7D; [0062-0063]) and is electrically connected at a second end to a contact of the substrate (499; see Figs. 7A-7D; [0071]).
Regarding claim 4, Chang teaches all of the features of claim 1.
Chang further teaches wherein: the first set of redistribution layers (375; see Figs. 7A-7D; [0062-0063]) includes a first set of conductive vias (see 375c; see Figs. 7A-7D, 10A; [0074]) interconnecting various first traces of the first set of metal layers, wherein the first set of conductive vias (see 375c; see Figs. 7A-7D, 10A; [0074]) are oriented along a first direction; and the second set of redistribution layers ({314, 502b}; see Figs.7B, 9; see [0067, 0073]; see [007], where it says “Junction circuit 375-3 may include a bonding via 375c connected to a second contact 502b-6 (e.g., combination copper trench/via), a bonding pad 375a formed over a metal-free area 650b (e.g., silicon area) of a second interface surface, and a bonding trench 375b that connects the bonding via 375c to the bonding pad 375a”; thus, it is construed that layers ({314, 502b} is redistribution layers) includes a second set of conductive vias ({502b-1, 502b-2}; see Figs.7B, 9; see [0067, 0073]; see [007], where it says “Junction circuit 375-3 may include a bonding via 375c connected to a second contact 502b-6 (e.g., combination copper trench/via), a bonding pad 375a formed over a metal-free area 650b (e.g., silicon area) of a second interface surface, and a bonding trench 375b that connects the bonding via 375c to the bonding pad 375a”; thus, it is construed that layers ({314, 502b} is redistribution layers) interconnecting various second traces of the second set of metal layers, wherein the second set of conductive vias ({502b-1, 502b-2}; see Figs.7B, 9; see [0067, 0073]; see [007], where it says “Junction circuit 375-3 may include a bonding via 375c connected to a second contact 502b-6 (e.g., combination copper trench/via), a bonding pad 375a formed over a metal-free area 650b (e.g., silicon area) of a second interface surface, and a bonding trench 375b that connects the bonding via 375c to the bonding pad 375a”; thus, it is construed that layers ({314, 502b} is redistribution layers) are oriented along a second direction that is perpendicular to the first direction.
Regarding claim 5, Chang teaches all of the features of claim 1.
Chang further teaches wherein the first die (501; see Figs. 7A-7D; [0061-0063, 0068-0070]) includes first active circuitry ([0023]), and the second die (502; see Figs. 7A-7D; [0066-0069]) includes one or more inductors, one or more capacitors, or both (see [0027]).
Regarding claim 6, Chang teaches all of the features of claim 1.
Chang further teaches wherein the first die (501; see Figs. 7A-7D; [0061-0063, 0068-0070]) includes first active circuitry, and the second die (502; see Figs. 7A-7D; [0066-0069]) includes second active circuitry (see [0023]).
Regarding claim 7, Chang teaches all of the features of claim 1.
Chang further teaches wherein the first die (501; see Figs. 7A-7D; [0061-0063, 0068-0070]) includes circuitry defining one or more processor cores (see [0023]) and the second die (502; see Figs. 7A-7D; [0066-0069]) includes circuitry defining a plurality of memory elements (see [0023]).
Regarding claim 8, Chang teaches all of the features of claim 1.
Chang further comprising a die stack that includes the second die (502; see Figs. 7A-7D; [0066-0069]) and the second set of redistribution layers ({314, 502b}; see Figs.7B, 9; see [0067, 0073]; see [007], where it says “Junction circuit 375-3 may include a bonding via 375c connected to a second contact 502b-6 (e.g., combination copper trench/via), a bonding pad 375a formed over a metal-free area 650b (e.g., silicon area) of a second interface surface, and a bonding trench 375b that connects the bonding via 375c to the bonding pad 375a”; thus, it is construed that layers ({314, 502b} is redistribution layers) and further includes one or more additional dies (a second occurrence of 502; see Figs. 7A-7D; [0066-0069]; a second occurrence of die 502 from the plurality of dies 502,) and one or more additional sets of redistribution layers (502; see Figs. 7A-7D; [0066-0069]; a second occurrence of die 502 from the plurality of dies 502), wherein each of the one or more additional sets of redistribution layers (a second occurrence of {314, 502b}; see Figs.7B, 9; see [0067, 0073]; see [007], where it says “Junction circuit 375-3 may include a bonding via 375c connected to a second contact 502b-6 (e.g., combination copper trench/via), a bonding pad 375a formed over a metal-free area 650b (e.g., silicon area) of a second interface surface, and a bonding trench 375b that connects the bonding via 375c to the bonding pad 375a”; thus, it is construed that layers ({314, 502b} is redistribution layers) includes metal layers oriented along the second plane (Figs. 7A-7D; [0064-0071]).
Regarding claim 9, Chang teaches all of the features of claim 1.
Chang further teaches wherein the first die (501; see Figs. 7A-7D; [0061-0063, 0068-0070]) includes a first set of contacts (501b; see Figs. 7A-7D; [0070]) on a first surface that is parallel to the first plane (Figs. 7A-7D; [0064-0071]) and the second die (502; see Figs. 7A-7D; [0066-0069]) includes a second set of contacts on a second surface that is parallel to the second plane (Figs. 7A-7D; [0064-0071]).
Regarding claim 10, Chang teaches all of the features of claim 9.
Chang further comprising a third die (502; see Figs. 7A-7D; [0066-0069]; a second occurrence of die 502 from the plurality of dies 502) disposed between the first set of redistribution layers (375; see Figs. 7A-7D; [0062-0063]) and the substrate (499; see Figs. 7A-7D; [0071]), the third die (502; see Figs. 7A-7D; [0066-0069]; a second occurrence of die 502 from the plurality of dies 502) including a third set of contacts on a third surface that is parallel to the first plane.
Regarding claim 11, Chang teaches all of the features of claim 1.
Chang further comprising a mold compound (460; see Figs. 7A-7D; [0065]) disposed between the first set of redistribution layers (375; see Figs. 7A-7D; [0062-0063]) and the substrate (499; see Figs. 7A-7D; [0071]) and at least partially encapsulating the second die (502; see Figs. 7A-7D; [0066-0069]) and the second set of redistribution layers ({314, 502b}; see Figs.7B, 9; see [0067, 0073]; see [007], where it says “Junction circuit 375-3 may include a bonding via 375c connected to a second contact 502b-6 (e.g., combination copper trench/via), a bonding pad 375a formed over a metal-free area 650b (e.g., silicon area) of a second interface surface, and a bonding trench 375b that connects the bonding via 375c to the bonding pad 375a”; thus, it is construed that layers ({314, 502b} is redistribution layers).
Regarding claim 12, Chang teaches all of the features of claim 11.
Chang further comprising one or more through mold vias (vias/traces from {314, 502b}; see Figs.7B, 9; see [0067, 0073]; see [007], where it says “Junction circuit 375-3 may include a bonding via 375c connected to a second contact 502b-6 (e.g., combination copper trench/via), a bonding pad 375a formed over a metal-free area 650b (e.g., silicon area) of a second interface surface, and a bonding trench 375b that connects the bonding via 375c to the bonding pad 375a”; thus, it is construed that layers ({314, 502b} is redistribution layers) extending through the mold compound (460; see Figs. 7A-7D; [0065]), wherein each through mold via (vias/traces from {314, 502b}; see Figs.7B, 9; see [0067, 0073]; see [007], where it says “Junction circuit 375-3 may include a bonding via 375c connected to a second contact 502b-6 (e.g., combination copper trench/via), a bonding pad 375a formed over a metal-free area 650b (e.g., silicon area) of a second interface surface, and a bonding trench 375b that connects the bonding via 375c to the bonding pad 375a”; thus, it is construed that layers ({314, 502b} is redistribution layers) electrically connects a contact of the substrate (499; see Figs. 7A-7D; [0071]) to a contact of the first set of redistribution layers (375; see Figs. 7A-7D; [0062-0063]).
Regarding claim 13, Chang teaches a device (see the entire document, specifically Fig. 1+; [0006+], and as cited below), comprising:
forming a structure that includes a substrate (499; see Figs. 7A-7D; [0071]),
a first set of redistribution layers (375; see Figs. 7A-7D; [0062-0063]) physically and electrically connected to a first die (501; see Figs. 7A-7D; [0061]), and a second set of redistribution layers ({314, 502b}; see Figs.7B, 9; see [0067, 0073]; see [007], where it says “Junction circuit 375-3 may include a bonding via 375c connected to a second contact 502b-6 (e.g., combination copper trench/via), a bonding pad 375a formed over a metal-free area 650b (e.g., silicon area) of a second interface surface, and a bonding trench 375b that connects the bonding via 375c to the bonding pad 375a”; thus, it is construed that layers ({314, 502b} is redistribution layers) interconnected with the first set of redistribution layers (375; see Figs. 7A-7D; [0062-0063]),
wherein the first set of redistribution layers (375; see Figs. 7A-7D; [0062-0063]) includes a first set of metal layers (see Figs. 7A-7D; [0062-0063, 0069-0070]) oriented along a first plane,
the second set of redistribution layers ({314, 502b}; see Figs.7B, 9; see [0067, 0073]; see [007], where it says “Junction circuit 375-3 may include a bonding via 375c connected to a second contact 502b-6 (e.g., combination copper trench/via), a bonding pad 375a formed over a metal-free area 650b (e.g., silicon area) of a second interface surface, and a bonding trench 375b that connects the bonding via 375c to the bonding pad 375a”; thus, it is construed that layers ({314, 502b} is redistribution layers) includes a second set of metal layers ({314, 502b}; see Figs.7B, 9; see [0067, 0073]; see [007], where it says “Junction circuit 375-3 may include a bonding via 375c connected to a second contact 502b-6 (e.g., combination copper trench/via), a bonding pad 375a formed over a metal-free area 650b (e.g., silicon area) of a second interface surface, and a bonding trench 375b that connects the bonding via 375c to the bonding pad 375a”; thus, it is construed that layers ({314, 502b} is redistribution layers) oriented along a second plane that is non-parallel with respect to the first plane, and the substrate includes a third set of metal layers (another occurrence of {314, 502b}; see Figs.7B, 9; see [0067, 0073]; see [007], where it says “Junction circuit 375-3 may include a bonding via 375c connected to a second contact 502b-6 (e.g., combination copper trench/via), a bonding pad 375a formed over a metal-free area 650b (e.g., silicon area) of a second interface surface, and a bonding trench 375b that connects the bonding via 375c to the bonding pad 375a”; thus, it is construed that layers ({314, 502b} is redistribution layers) oriented along a third plane that is parallel to the second plane; and electrically connecting a second die (502; see Figs. 7A-7D; [0066-0069]) to the second set of redistribution layers ({314, 502b}; see Figs.7B, 9; see [0067, 0073]; see [007], where it says “Junction circuit 375-3 may include a bonding via 375c connected to a second contact 502b-6 (e.g., combination copper trench/via), a bonding pad 375a formed over a metal-free area 650b (e.g., silicon area) of a second interface surface, and a bonding trench 375b that connects the bonding via 375c to the bonding pad 375a”; thus, it is construed that layers ({314, 502b} is redistribution layers) to define conductive paths between the first die (501; see Figs. 7A-7D; [0061]) and the second die (502; see Figs. 7A-7D; [0066-0069]) through the second set of redistribution layers ({314, 502b}; see Figs.7B, 9; see [0067, 0073]; see [007], where it says “Junction circuit 375-3 may include a bonding via 375c connected to a second contact 502b-6 (e.g., combination copper trench/via), a bonding pad 375a formed over a metal-free area 650b (e.g., silicon area) of a second interface surface, and a bonding trench 375b that connects the bonding via 375c to the bonding pad 375a”; thus, it is construed that layers ({314, 502b} is redistribution layers) and the first set of redistribution layers (375; see Figs. 7A-7D; [0062-0063]).
Regarding claim 14, Chang teaches all of the features of claim 13.
Chang further teaches wherein the second plane is orthogonal to the first plane (see Figs. 7A-7D; see [0065-0071]).
Regarding claim 15, Chang teaches all of the features of claim 13.
Chang further teaches wherein forming the structure includes: exposing ends of conductors of the first set of redistribution layers (375; see Figs. 7A-7D; [0062-0063]); and forming conductors of the second set of redistribution layers ({314, 502b}; see Figs.7B, 9; see [0067, 0073]; see [007], where it says “Junction circuit 375-3 may include a bonding via 375c connected to a second contact 502b-6 (e.g., combination copper trench/via), a bonding pad 375a formed over a metal-free area 650b (e.g., silicon area) of a second interface surface, and a bonding trench 375b that connects the bonding via 375c to the bonding pad 375a”; thus, it is construed that layers ({314, 502b} is redistribution layers) on the ends of the conductors of the first set of redistribution layers (375; see Figs. 7A-7D; [0062-0063]).
Regarding claim 16, Chang teaches all of the features of claim 13.
Chang further comprising forming a die stack that includes the first die (501; see Figs. 7A-7D; [0061]), the first set of redistribution layers (375; see Figs. 7A-7D; [0062-0063]), (a second occurrence of 502; see Figs. 7A-7D; [0066-0069]; a second occurrence of die 502 from the plurality of dies 502,) and one or more additional sets of redistribution layers (502; see Figs. 7A-7D; [0066-0069]; a second occurrence of die 502 from the plurality of dies 502), wherein each of the one or more additional sets of redistribution layers (a second occurrence of {314, 502b}; see Figs.7B, 9; see [0067, 0073]; see [007], where it says “Junction circuit 375-3 may include a bonding via 375c connected to a second contact 502b-6 (e.g., combination copper trench/via), a bonding pad 375a formed over a metal-free area 650b (e.g., silicon area) of a second interface surface, and a bonding trench 375b that connects the bonding via 375c to the bonding pad 375a”; thus, it is construed that layers ({314, 502b} is redistribution layers).
Regarding claim 17, Chang teaches all of the features of claim 13.
Chang further comprising forming the substrate (499; see Figs. 7A-7D; [0071]) as a third set of redistribution layers (a second occurrence of {314, 502b}; see Figs.7B, 9; see [0067, 0073]; see [007], where it says “Junction circuit 375-3 may include a bonding via 375c connected to a second contact 502b-6 (e.g., combination copper trench/via), a bonding pad 375a formed over a metal-free area 650b (e.g., silicon area) of a second interface surface, and a bonding trench 375b that connects the bonding via 375c to the bonding pad 375a”; thus, it is construed that layers ({314, 502b} is redistribution layers), wherein the second set of redistribution layers ({314, 502b}; see Figs.7B, 9; see [0067, 0073]; see [007], where it says “Junction circuit 375-3 may include a bonding via 375c connected to a second contact 502b-6 (e.g., combination copper trench/via), a bonding pad 375a formed over a metal-free area 650b (e.g., silicon area) of a second interface surface, and a bonding trench 375b that connects the bonding via 375c to the bonding pad 375a”; thus, it is construed that layers ({314, 502b} is redistribution layers) are physically and electrically connected to first ends of the first set of redistribution layers (375; see Figs. 7A-7D; [0062-0063]) and the third set of redistribution layers (a second occurrence of {314, 502b}; see Figs.7B, 9; see [0067, 0073]; see [007], where it says “Junction circuit 375-3 may include a bonding via 375c connected to a second contact 502b-6 (e.g., combination copper trench/via), a bonding pad 375a formed over a metal-free area 650b (e.g., silicon area) of a second interface surface, and a bonding trench 375b that connects the bonding via 375c to the bonding pad 375a”; thus, it is construed that layers ({314, 502b} is redistribution layers) are physically and electrically connected to second ends of the first set of redistribution layers (375; see Figs. 7A-7D; [0062-0063]).
Regarding claim 18, Chang teaches all of the features of claim 13.
Chang further teaches wherein the structure further comprises a third die (a second occurrence of 502; see Figs. 7A-7D; [0066-0069]) disposed between the substrate (499; see Figs. 7A-7D; [0071]) to and the second set of redistribution layers ({314, 502b}; see Figs.7B, 9; see [0067, 0073]; see [007], where it says “Junction circuit 375-3 may include a bonding via 375c connected to a second contact 502b-6 (e.g., combination copper trench/via), a bonding pad 375a formed over a metal-free area 650b (e.g., silicon area) of a second interface surface, and a bonding trench 375b that connects the bonding via 375c to the bonding pad 375a”; thus, it is construed that layers ({314, 502b} is redistribution layers) and having a face oriented along a plane parallel to the second plane (see Figs. 7A-7D).
Regarding claim 19, Chang teaches all of the features of claim 13.
Chang further teaches wherein the structure further comprises a mold compound (460; see Figs. 7A-7D; [0065]) disposed between the second set of redistribution layers ({314, 502b}; see Figs.7B, 9; see [0067, 0073]; see [007], where it says “Junction circuit 375-3 may include a bonding via 375c connected to a second contact 502b-6 (e.g., combination copper trench/via), a bonding pad 375a formed over a metal-free area 650b (e.g., silicon area) of a second interface surface, and a bonding trench 375b that connects the bonding via 375c to the bonding pad 375a”; thus, it is construed that layers ({314, 502b} is redistribution layers) and the substrate (499; see Figs. 7A-7D; [0071]) to at least partially encapsulate the first die (501; see Figs. 7A-7D; [0061]) and the first set of redistribution layers (375; see Figs. 7A-7D; [0062-0063]).
Regarding claim 20, Chang teaches all of the features of claim 19.
Chang further teaches wherein the structure further comprises one or more through mold vias (vias/traces from {314, 502b}; see Figs.7B, 9; see [0067, 0073]; see [007], where it says “Junction circuit 375-3 may include a bonding via 375c connected to a second contact 502b-6 (e.g., combination copper trench/via), a bonding pad 375a formed over a metal-free area 650b (e.g., silicon area) of a second interface surface, and a bonding trench 375b that connects the bonding via 375c to the bonding pad 375a”; thus, it is construed that layers ({314, 502b} is redistribution layers) extending through the mold compound (460; see Figs. 7A-7D; [0065]) and electrically connecting one or more contacts of the substrate (499; see Figs. 7A-7D; [0071]) to one or more contacts of the second set of redistribution layers ({314, 502b}; see Figs.7B, 9; see [0067, 0073]; see [007], where it says “Junction circuit 375-3 may include a bonding via 375c connected to a second contact 502b-6 (e.g., combination copper trench/via), a bonding pad 375a formed over a metal-free area 650b (e.g., silicon area) of a second interface surface, and a bonding trench 375b that connects the bonding via 375c to the bonding pad 375a”; thus, it is construed that layers ({314, 502b} is redistribution layers).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Omar Mojaddedi whose telephone number is 313-446-6582. The examiner can normally be reached on Monday – Friday, 8:00 a.m. to 4:00 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado, can be reached on 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/OMAR F MOJADDEDI/Examiner, Art Unit 2898
Prosecution Insights