DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant's amendments filed June 29, 2026. Claims 1-3, and 6 have been amended. Claims 7-10 have been added. Claims 4-5 have been canceled. Currently, claims 1-3, and 6-10 are pending.
Response to Arguments
Applicant's arguments filed June 29, 2026 have been fully considered but they are not persuasive.
Applicant asserts that the combination of Yoshihara et al. (US 20210193592 A1) and of Soyano et al. (US 20170213777 A1) fail to disclose the limitations of newly amended claim 1. Specifically, that “the pillow part 521 of Yoshihara does not constitute a substrate including an insulating layer” and Soyano fails to disclose “a thermal conductivity of the connecting substrate is less than a thermal conductivity of an insulated circuit board on which the semiconductor chip is disposed”.
The Examiner respectfully disagrees with these assertions. Firstly, the claims do not require that the connecting substrate, which was mapped to the pillow part 521 of Yoshihara, include an insulating layer.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e. the connecting substrate including an insulating layer) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Further, Soyano was not relied upon to disclose a thermal conductivity of the connecting substrate is less than a thermal conductivity of an insulated circuit board on which the semiconductor chip is disposed as this was disclosed by the materials of Yoshihara. However, assuming that one of ordinary skill in the art would replace the connecting substrate of Yoshihara with the connecting substrate of Soyano, rather than incorporating the structure, Soyano discloses that the connecting substrate comprises a ceramic silicon nitride which has a thermal conductivity that is less than the thermal conductivity of the insulated circuit board disclosed by Yoshihara (see Silicon Nitride Material Data).
Therefore, the combination discloses the limitations of newly amended claim 1. The rejection of newly amended claim 1 in view of Yoshihara and Soyano is presented herein as appropriate.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 9 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 9, the claim recites the limitation “the connecting substrate includes resin material” in lines 1-2 which does not have support in the disclosure. The specification discloses, in ¶ [0029-0030], that the connecting substrate is made up of an insulating plate, a metallic foil and several wiring layers. There is no disclosure that supports the connecting substrate including a resin material.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshihara (US 20210193592 A1) in view of Soyano (US 20170213777 A1).
Regarding claim 1, Figs. 3 and 12 of Yoshihara disclose a semiconductor device (Fig. 3, semiconductor device A10, ¶ [0061]) comprising:
a semiconductor chip (Fig. 3, first semiconductor elements 40A, ¶ [0062]);
a bonding wire (Fig. 12, wire part 522, ¶ [0090]) electrically connected to an electrode (Fig. 12, first electrode 41, ¶ [0083]) provided on the semiconductor chip (40A); and
a connecting substrate (Fig. 12, pillow part 521, ¶ [0090]) jointed to the electrode (41) of the semiconductor chip (40A),
wherein a thermal expansion coefficient of the connecting substrate (521) is equal to a thermal expansion coefficient of the bonding wire (522) (Yoshihara discloses, in ¶ [0091-0092], that second layer 521B and wire part can both be made of aluminum. Therefore, disclosing that the connecting substrate and the bonding wire have the same thermal expansion coefficient and the difference is zero), or the thermal expansion coefficient of the connecting substrate (521) is within a range of the thermal expansion coefficient of the bonding wire (522) or less and a first thermal expansion coefficient or greater,
a difference between the first thermal expansion coefficient and the thermal expansion coefficient of the bonding wire (522) is a predetermined value (Yoshihara discloses, in ¶ [0091-0092], that second layer 521B and wire part can both be made of aluminum. Therefore, disclosing that the connecting substrate and the bonding wire have the same thermal expansion coefficient and the difference is zero),
the bonding wire (522) is jointed (Fig. 12, bonding layer 49, ¶ [0088]) to the connecting substrate (521) to be electrically connected to the electrode (41) via the connecting substrate (521),
a thermal conductivity of the connecting substrate (521) is less than a thermal conductivity of an insulated circuit board (Fig. 10, insulating support member 10, ¶ [0064]) on which the semiconductor chip (40A) is disposed (Yoshihara discloses the connecting substrate contains an alloy such as Kovar (see Yoshihara, ¶ [0091]) and the insulated circuit board is a ceramic such as aluminum nitride (AlN) (see Yoshihara, ¶ [0064]). The thermal conductivity of Kovar is known to be approximately 17.3 W/mK (see Kovar Material Data) and the thermal conductivity of AlN is known to be 180 W/mK (see Aluminum Material Data), and
the connecting substrate (521) includes:
a substrate (Fig. 12, first layer 521A, ¶ [0091]) having a first main surface (top surface in Fig. 12), a second main surface (bottom surface in Fig. 12).
Yoshihara fails to disclose wherein the connecting substrate includes:
at least one through hole penetrating between the first main surface and the second main surface;
a first wiring layer that is conductive, the first wiring layer being provided on the first main surface and being jointed to the bonding wire;
a second wiring layer that is conductive, the second wiring layer being provided on the second main surface and being jointed to the electrode of the semiconductor chip; and
a third wiring layer that is conductive, the third wiring layer being provided on a wall surface of the through hole and coupling the first wiring layer and the second wiring layer to each other.
In the similar field of endeavor of semiconductor devices, Figs. 7-8 of Soyano disclose wherein the connecting substrate (Fig. 7, circuit board (second insulating substrate) 14, ¶ [0030]) includes:
at least one through hole (Fig. 8, penetration holes 14e, ¶ [0031]) penetrating between the first main surface (top surface in Fig. 7) and the second main surface (bottom surface in Fig. 7);
a first wiring layer (Fig. 7, circuit pattern 14c, ¶ [0030]) that is conductive, the first wiring layer (14c) being provided on the first main surface (top surface in Fig. 7) and being jointed to the bonding wire (25);
a second wiring layer (Fig. 7, circuit pattern 14b, ¶ [0030]) that is conductive, the second wiring layer (14b) being provided on the second main surface (bottom surface in Fig. 7) and being jointed to the electrode of the semiconductor chip (Fig. 7, semiconductor chip 13, ¶ [0029]); and
a third wiring layer (Fig. 7, copper pellets 14d, ¶ [0031]) that is conductive, the third wiring layer (14d) being provided on a wall surface of the through hole (14e) and coupling the first wiring layer (14c) and the second wiring layer (14b) to each other (“the circuit pattern 14b and the circuit pattern 14c are stuck on both surfaces of the ceramic plate 14a and are connected to each other by the copper pellets 14d disposed in the penetration holes 14e”, ¶ [0031]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Yoshihara with the connecting substrate as disclosed by Soyano, to reduce stress on the semiconductor chip (see Soyano, ¶ [0035]).
Regarding claim 7, Yoshihara and Soyano disclose the semiconductor device according to claim 1 as applied above, and Yoshihara further discloses wherein thermal conductivity of the substrate (521A) of the connecting substrate (521) is less than or equal to one-tenth of the thermal conductivity of the insulated circuit board (10) Yoshihara discloses the substrate is an alloy such as Kovar (see Yoshihara, ¶ [0091]) and the insulated circuit board is a ceramic such as aluminum nitride (AlN) (see Yoshihara, ¶ [0064]). The thermal conductivity of Kovar is known to be approximately 17.3 W/mK (see Kovar Material Data) and the thermal conductivity of AlN is known to be 180 W/mK (see Aluminum Material Data).
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshihara (US 20210193592 A1) and Soyano (US 20170213777 A1) in further view of Huang et al. (US 20160233179 A1) herein after “Huang”.
Regarding claim 2, Yoshihara and Soyano together disclose the semiconductor device according to claim 1 as applied above, but Yoshihara and Soyano fail to explicitly disclose wherein with the bonding wire and electrode jointed to each other, a shear strength of a connection between the connecting substrate and the electrode is greater than a shear strength of a connection between the bonding wire and the electrode in a state in which the bonding wire and the electrode.
In the similar field of endeavor of semiconductor devices, Figs. 1 and 10 of Huang discloses wherein with the bonding wire (Fig. 1, conductive wires 145, ¶ [0014]) and electrode (Fig. 10, contact regions 113, ¶ [0013]) jointed to each other, a shear strength of a connection between the connecting substrate (Fig. 10, buffer layer 1050, ¶ [0037]) and the electrode (113) is greater than shear strength of a connection between the bonding wire (Fig. 1, conductive wires 145, ¶ [0014]) and the electrode (113) (Huang discloses, in ¶ [0037] and Fig. 10, that the connecting substrate 1050 increases the strength and stiffness of the connection when compared with direct wire bonding, described in ¶ [0013-0014] and Fig. 1).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Yoshihara with the interconnect structure as disclosed by Huang, to create a reliable electrical and mechanical interconnection (see Huang. ¶ [0019]).
Regarding claim 3, Yoshihara, Soyano and Huang together disclose the semiconductor device of claim 2 as applied above, and Figs. 9 and 12 of Yoshihara further disclose comprising:
the insulated circuit board (10) on which the semiconductor chip (40A) is disposed; and
a wiring member (Fig. 9, first leads 51A, ¶ [0062]) having a plate-shape and that electrically connects the electrode (41) and the insulated circuit board (10) to each other,
wherein a jointing material (“The second bonding layer 49 is made of a lead-free solder mainly composed of tin (Sn)”, ¶ [0088]) used to join the connecting substrate (521) and the electrode (41) to each other is used to join the wiring member (51A) and the electrode (41) to each other (“The first bonding layer 29 is made of a lead-free solder mainly composed of tin (Sn)”, ¶ [0086]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshihara (US 20210193592 A1) and Soyano (US 20170213777 A1) in further view of Groenhuis et al. (US 20150287666 A1) herein after “Groenhuis”.
Regarding claim 6, Yoshihara and Soyano together disclose the semiconductor device according to claim 1 as applied above, but Yoshihara fails to disclose wherein an opening shape of the through hole viewed from the first main surface is an elongated circular shape.
In the similar field of endeavor of semiconductor devices, Fig. 8 of Soyano discloses wherein an opening shape of the through hole (14e) viewed from the first main surface (top surface in Fig. 7) is an circular shape.
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Yoshihara with the through holes as disclosed by Soyano, to reduce stress on the semiconductor chip (see Soyano, ¶ [0035]).
Soyano fails to disclose the through hole is an elongated circular shape.
In the similar field of endeavor of semiconductor components, Fig. 2a of Groenhuis discloses the through hole (Fig. 2a, through hole 26, ¶ [002]) is an elongated circular shape (shown in Fig. 2a).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Yoshihara in view of Soyano with the elongated circular through holes as disclosed by Groenhuis, to increase production quality and reliability (see Groenhuis, ¶ [0023-0024]) and/or because it has been ruled that changes of shape are prima facie obvious absent persuasive evidence that the particular configuration is significant (MPEP 2144.04(IV)(B).
Claims 8-10 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshihara (US 20210193592 A1) and Soyano (US 20170213777 A1) in further view of Nomann et al. (US 20180330967 A1) herein after “Nomann”.
Regarding claim 8, Yoshihara and Soyano together disclose the semiconductor device according to claim 1 as applied above, but Yoshihara and Soyano fail to disclose wherein the substrate of the connecting substrate is a printed circuit board.
In the similar field of endeavor of semiconductor module arrangements, Fig. 1 of Nomann discloses wherein the substrate (Fig. 1, dielectric insulation layer 11, ¶ [0015]) of the connecting substrate (Fig. 1, separate substrate 10, ¶ [0015]) is a printed circuit board (“The separate substrate 10 may also be a conventional printed circuit board (PCB) having a non-ceramic dielectric insulation layer 11”, ¶ [0016]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to substitute the connecting substrate of Yoshihara for the printed circuit board as disclosed by Nomann. The claimed connecting substrate structure was known in the prior art and one skilled in the art could have combined the structure of Yoshihara with the PCB of Nomann as claimed with no change in their respective functions, and the combination would have yielded the predictable result of creating a stable contact structure. See KSR International Co. V. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 9, Yoshihara, Soyano and Nomann together disclose the semiconductor device according to claim 8 as applied above, but Yoshihara and Soyano fail to disclose wherein the connecting substrate includes resin material.
In the similar field of endeavor of semiconductor module arrangements, Fig. 1 of Nomann discloses wherein the connecting substrate (10) includes resin material (“a non-ceramic dielectric insulation layer 11 may consist of or include a cured resin”, ¶ [0016]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Yoshihara with the material as disclosed by Nomann, to provide a suitable dielectric layer (see Nomann, ¶ [0016]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 10, Yoshihara, Soyano and Nomann together disclose the semiconductor device according to claim 8 as applied above, but Yoshihara and Soyano fail to disclose wherein the printed circuit board is either a rigid board or a flexible board.
In the similar field of endeavor of semiconductor module arrangements, Fig. 1 of Nomann discloses wherein the printed circuit board (10) is either a rigid board or a flexible board (“The separate substrate 10 may also be a conventional printed circuit board (PCB)”, ¶ [0016]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to substitute the connecting substrate of Yoshihara for the printed circuit board as disclosed by Nomann. The claimed connecting substrate structure was known in the prior art and one skilled in the art could have combined the structure of Yoshihara with the PCB of Nomann as claimed with no change in their respective functions, and the combination would have yielded the predictable result of creating a stable contact structure. See KSR International Co. V. Teleflex Inc., 82 USPQ2d 1385 (2007).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.A.N./ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
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