DETAILED ACTION
This correspondence is in response to the communications received June 15, 2026. Claims 1, 3-9, 11-12 and 14-17 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 2, 10 and 13 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species I (directed to a first embodiment of a semiconductor transistor that is a NMOS transistor), there being no allowable generic or linking claim. Election was made without traverse in the reply filed on June 15, 2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 and the claims that depend therefrom, are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The recitation, “forming a gate region within the semiconductor substrate”, renders the claim indefinite, as it is unclear how the gate can be within, or inside of the substrate, when it is only clearly shown on top of the substrate. For purposes of examination, the limitation will be interpreted to mean that the gate region is formed on top of the substrate.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, the Applicant discloses in Fig. 21, a semiconductor transistor comprising:
a source region (“12 both source and drain regions are formed by ion-implanting p-type dopants into an n-well”, ¶ 0003),
a drain region (“12 both source and drain regions are formed by ion-implanting p-type dopants into an n-well”, ¶ 0003), and
a channel region between the source region and the drain region (portion of n-well between the p-type source and drain regions); and
a gate region over the channel region (localized region immediately above 331),
wherein the gate region comprises a gate dielectric layer (331) on the channel region and an epitaxial doped semiconductor layer (“epitaxial silicon gate of the PMOS transistor”, ¶ 0098, “The high dopant activation concentration of the in-situ doped N+/P+ silicon 3322 can reduce polysilicon depletion effect, reduce the thickness of the gate dielectric layer 331, and improve Ion and gate control capability.”, ¶ 0033) over the gate dielectric layer (over 331).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 6, 11, 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Kuroi et al. (US 6,300,664) in view of Balakrishnan et al. (US 2019/0067280).
Elected embodiment: Species II, PMOS transistor
It is noted that the “effective date” is a mix of the following.
Prov: June 2, 2022 (up to Fig. 15B)
CIP: May 31, 2023 (up to Fig. 15B)
Prov: January 9, 2024 (only support for the dopant activation aspects)
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Regarding claim 1, the prior art of Kuroi discloses in Figs. 1 and 2, a semiconductor transistor (“FIG. 1 is a sectional view showing a PMOS transistor”, col. 10, line 55) comprising:
a source region (the ‘source’ portion of the “Source/drain regions 6”, col. 14, line 54),
a drain region (the ‘drain’ portion of the “Source/drain regions 6”, col. 14, line 54), and
a channel region (“channel region 10”, col. 14, line 57) between the source region and the drain region (10 between the two 6 regions); and
a gate region (combination of, “P+ -type gate electrode 35”, col. 14, lines 61-62, and “gate oxide film 36”, col. 14, lines 59) over the channel region (35/36 over 10),
wherein the gate region (35) comprises a gate dielectric layer (“gate oxide film 36”, col. 14, lines 59, where the “oxide” is a type of dielectric material) on the channel region (36 on 10).
Kuroi fails to disclose, “wherein the gate region comprises … an epitaxial doped semiconductor layer over the gate dielectric layer.”
Balakrishnan discloses in ¶ 0081, “The epitaxially grown gate region 158 can be in-situ doped during epitaxial growth processes, and dopants may include, for example, an n-type dopant selected from a group V element hydride including, but not limited to, arsine (AsH.sub.3), and phosphine (PH.sub.3), and a p-type dopant selected from a group III element hydride, including, but not limited to, diborane gas at various concentrations. For example, in a non-limiting example, a dopant concentration range may be e19/cm.sup.3 to e20/cm.sup.3, from 1e19/cm.sup.3 to 4e20/cm.sup.3 preferred. The gate region 158 can include, but is not necessarily limited to, silicon (Si), silicon germanium (SiGe), or other semiconductor material.”, ¶ 0080, “The gate region 158 can be formed by a gate on channel epitaxy process, where highly doped semiconductor material forming the gate is epitaxially grown onto the outer surface of the channel region 140.”
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein the gate region comprises … an epitaxial doped semiconductor layer over the gate dielectric layer.”, as disclosed by Balakrishnan in the system of Kuroi, for the purpose of providing a materially more compatible gate structure with similar material to channel at a high concentration for high electron mobility performance capability. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 3, the prior art of Kuroi et al. disclose the semiconductor transistor in claim 1, wherein the semiconductor transistor is a PMOS transistor (“FIG. 1 is a sectional view showing a PMOS transistor”, col. 10, line 55), the epitaxial doped semiconductor layer is an epitaxial doped silicon layer (the combination rejection of claim 1 addresses this aspect, see above for details, addressed by Balakrishnan states, ¶ 0081), and the dopant activation concentration of the epitaxial doped silicon layer is not less than 8 x1019/cm3 (Fig. 2 of Kuroi discloses a dopant concentration that is at and far above the quoted value, further Balakrishnan states, ¶ 0081, “a dopant concentration range may be e19/cm.sup.3 to e20/cm.sup.3, from 1e19/cm.sup.3 to 4e20/cm.sup.3 preferred.).
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Regarding claim 6, the prior art of Kuroi discloses in Figs. 1 and 2, a method to manufacture a semiconductor transistor (see title, “Semiconductor Device And Method Of Fabricating The Same”, and, “FIG. 1 is a sectional view showing a PMOS transistor”, col. 10, line 55) comprising:
preparing a semiconductor substrate (“silicon substrate 1”, col. 14, line 52);
forming a gate region (the gate region can include the combination “gate electrode 35”, col. 14, line 58, and “gate oxide film 36”, col. 14, lines 59) within the semiconductor substrate (35/36 on 1),
wherein the gate region comprises a doped semiconductor layer (“P+-type gate electrode 35”, col. 14, line 58, where the dopants are denoted by the “P+-type” portion); and
forming a source region (the ‘source’ portion of the “Source/drain regions 6”, col. 14, line 54) and a drain region (the ‘drain’ portion of the “Source/drain regions 6”, col. 14, line 54),
wherein the gate region is between the source region and the drain region (35/36 are laterally between the two 6).
Kuroi does not disclose, “wherein the gate region comprises an epitaxial doped semiconductor layer”.
Balakrishnan discloses in ¶ 0081, “The epitaxially grown gate region 158 can be in-situ doped during epitaxial growth processes, and dopants may include … a group III element … a dopant concentration range may be e19/cm.sup.3 to e20/cm.sup.3, from 1e19/cm.sup.3 to 4e20/cm.sup.3 preferred. The gate region 158 can include, but is not necessarily limited to, silicon (Si), silicon germanium (SiGe), or other semiconductor material.”, ¶ 0080, “The gate region 158 can be formed by a gate on channel epitaxy process, where highly doped semiconductor material forming the gate is epitaxially grown onto the outer surface of the channel region 140.”
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein the gate region comprises an epitaxial doped semiconductor layer”, as disclosed by Balakrishnan in the system of Kuroi, for the purpose of providing a materially more compatible gate structure with similar material to channel at a high concentration for high electron mobility performance capability. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 11, the prior art of Kuroi et al. disclose the semiconductor transistor in claim 6, and wherein the semiconductor transistor is a PMOS transistor (Kuroi discloses, “FIG. 1 is a sectional view showing a PMOS transistor”, col. 10, line 55), however, Kuroi does not disclose, “the epitaxial doped semiconductor layer is an epitaxial doped silicon layer, and the dopant activation concentration of the epitaxial doped silicon layer is not less than 8 x1019/cm3”.
Balakrishnan discloses, the epitaxial doped semiconductor layer is an epitaxial doped silicon layer, and the dopant activation concentration of the epitaxial doped silicon layer is not less than 8 x1019/cm3 (¶ 0081, “The epitaxially grown gate region 158 can be in-situ doped during epitaxial growth processes, and dopants may include … a group III element … a dopant concentration range may be e19/cm.sup.3 to e20/cm.sup.3, from 1e19/cm.sup.3 to 4e20/cm.sup.3 preferred. The gate region 158 can include, but is not necessarily limited to, silicon (Si), silicon germanium (SiGe), or other semiconductor material.”, ¶ 0080, “The gate region 158 can be formed by a gate on channel epitaxy process, where highly doped semiconductor material forming the gate is epitaxially grown onto the outer surface of the channel region 140.”).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “the epitaxial doped semiconductor layer is an epitaxial doped silicon layer, and the dopant activation concentration of the epitaxial doped silicon layer is not less than 8 x1019/cm3”, as disclosed by Balakrishnan in the system of Kuroi, for the purpose of providing a materially more compatible gate structure with similar material to channel at a high concentration for high electron mobility performance capability. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
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Regarding claim 15, the prior art of Kuroi discloses in Figs. 1 and 2, a semiconductor transistor (“FIG. 1 is a sectional view showing a PMOS transistor”, col. 10, line 55) comprising:
a source region (the ‘source’ portion of the “Source/drain regions 6”, col. 14, line 54),
a drain region (the ‘drain’ portion of the “Source/drain regions 6”, col. 14, line 54), and
a channel region (“channel region 10”, col. 14, line 57) between the source region and the drain region (10 laterally between the two 6); and
a gate region (combination of gate electrode, “P+ -type gate electrode 35”, col. 14, lines 61-62, and gate oxide, “gate oxide film 36”, col. 14, line 59) over the channel region (over 10),
wherein the gate region comprises a gate dielectric layer (“gate oxide film 36”, col. 14, line 59, where the “oxide” is a type of dielectric material) on the channel region (36 on 10) and a doped semiconductor layer (gate electrode, “P+ -type gate electrode 35”, col. 14, lines 61-62, where the + sign signifies an elevated, high or “highly” dopant concentration) over the gate dielectric layer (35 on 36);
wherein (“FIG. 1 is a sectional view showing a PMOS transistor”, col. 10, line 55).
Kuroi does not disclose, “the dopant activation concentration of the epitaxial doped silicon layer is not less than 8 x1019/cm3.”
Balakrishnan discloses in ¶ 0081, “The epitaxially grown gate region 158 can be in-situ doped during epitaxial growth processes, and dopants may include … a group III element … a dopant concentration range may be e19/cm.sup.3 to e20/cm.sup.3, from 1e19/cm.sup.3 to 4e20/cm.sup.3 preferred. The gate region 158 can include, but is not necessarily limited to, silicon (Si), silicon germanium (SiGe), or other semiconductor material.”, ¶ 0080, “The gate region 158 can be formed by a gate on channel epitaxy process, where highly doped semiconductor material forming the gate is epitaxially grown onto the outer surface of the channel region 140.”
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “the dopant activation concentration of the epitaxial doped silicon layer is not less than 8 x1019/cm3”, as disclosed by Balakrishnan in the system of Kuroi, for the purpose of providing a materially more compatible gate structure with similar material to channel at a high concentration for high electron mobility performance capability. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 16, the prior art of Kuroi et al. disclose the semiconductor transistor in claim 15, wherein the doped semiconductor layer is a doped silicon layer or a doped SiGe layer (Balakrishnan discloses in ¶ 0081, “The gate region 158 can include, but is not necessarily limited to, silicon (Si), silicon germanium (SiGe)”).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kuroi et al. (US 6,300,664) in view of Balakrishnan et al. (US 2019/0067280) in view of Hofmann et al. (US 2008/0191268).
Regarding claim 4, the prior art of Kuroi et al. disclose the semiconductor transistor in claim 1, however Kuroi does not disclose, “wherein the gate region further comprises a TiN layer and a Tungsten layer over the epitaxial doped semiconductor layer.”
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Hofmann discloses in Fig. 11C, wherein the gate region further comprises a TiN layer (“Ti/Tn” shown over “Poly-Si” gate portion, ¶ 0052) and a Tungsten layer over the epitaxial doped semiconductor layer (“W” shown over “Ti/Tn” shown over “Poly-Si” gate portion, ¶ 0052).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein the gate region further comprises a TiN layer and a Tungsten layer over the epitaxial doped semiconductor layer.”, as disclosed by Hofmann in the system of Kuroi, for the purpose of providing an upper layer gate electrode layer that can make a low resistance interface with a contact via, and a barrier layer to prevent migration of tungsten into the poly gate which would adversely effect the functionality of said poly gate. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kuroi et al. (US 6,300,664) in view of Balakrishnan et al. (US 2019/0067280) in view of Hofmann et al. (US 2008/0191268) in view of Cha et al. (US 2022/0285158).
Regarding claim 5, the prior art of Kuroi et al. disclose the semiconductor transistor in claim 4, however Kuroi does not disclose, “wherein the semiconductor transistor is a transistor in a peripheral circuit of DRAM.”
Cha discloses in ¶ 0094, “The peripheral circuit region PERI may include an NMOS region NMOS and a PMOS region PMOS. The cell region CELL may include a DRAM cell array or a NAND memory cell string. In this embodiment, the cell region CELL may be a part of a DRAM cell array.”
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein the semiconductor transistor is a transistor in a peripheral circuit of DRAM.”, as disclosed by Cha in the system of Kuroi, for the purpose of utilizing energy efficient CMOS transistors for use in a controller support role for the DRAM memory array. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claims 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Kuroi et al. (US 6,300,664) in view of Balakrishnan et al. (US 2019/0067280) in view of Ju et al. (US 2021/0407993) in view of Wu et al. (US 9,837,553).
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Regarding claim 12, the prior art of Kuroi discloses in Figs. 1 and 2, a semiconductor transistor (“FIG. 1 is a sectional view showing a PMOS transistor”, col. 10, line 55) comprising:
a source region (the ‘source’ portion of the “Source/drain regions 6”, col. 14, line 54),
a drain region (the ‘drain’ portion of the “Source/drain regions 6”, col. 14, line 54), and
a channel region (“channel region 10”, col. 14, line 57) between the source region and the drain region (10 laterally between the two 6); and
a gate region (combination of gate electrode, “P+ -type gate electrode 35”, col. 14, lines 61-62, and gate oxide, “gate oxide film 36”, col. 14, line 59) over the channel region (35 over 10),
wherein the gate region comprises a gate dielectric layer (“gate oxide film 36”, col. 14, line 59) on the channel region (36 on 10) and a highly doped semiconductor layer (gate electrode, “P+ -type gate electrode 35”, col. 14, lines 61-62, where the + sign signifies an elevated, high or “highly” dopant concentration) over the gate dielectric layer (35 on 36).
First, Kuroi does not disclose, “wherein a gate length of the gate region is not greater than 150 nm”.
Wu teaches in col. 5, lines 7-12, “the epitaxial source region 65a and drain region 65b can form a long channel device (e.g., gate length > nm), medium channel device (e.g., gate length of about 20 to 100 nm), “Wimpy” device (e.g., gate length of about 10 to 20 nm) and/or other devices (e.g., thick oxide devices with gate lengths of approximately 100 nm …”. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein a gate length of the gate region is not greater than 150 nm”, as disclosed by Wu in the system of Kuroi, for the purpose of utilizing devices with dimensions that are increasingly diminutive gate lengths which can increase device density per unit ara and further increase the device functionality. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Second, Kuroi does not disclose, “wherein the highly doped semiconductor layer within the gate length is a single crystalline layer, or along the gate length the highly doped semiconductor layer includes no more than three semiconductor grains.”
Balakrishnan discloses, the epitaxial doped semiconductor layer is an epitaxial doped silicon layer, and the dopant activation concentration of the epitaxial doped silicon layer is not less than 8 x1019/cm3 (¶ 0081, “The epitaxially grown gate region 158 can be in-situ doped during epitaxial growth processes, and dopants may include … a group III element … a dopant concentration range may be e19/cm.sup.3 to e20/cm.sup.3, from 1e19/cm.sup.3 to 4e20/cm.sup.3 preferred. The gate region 158 can include, but is not necessarily limited to, silicon (Si), silicon germanium (SiGe), or other semiconductor material.”, ¶ 0080, “The gate region 158 can be formed by a gate on channel epitaxy process, where highly doped semiconductor material forming the gate is epitaxially grown onto the outer surface of the channel region 140.”).
Ju teaches in ¶ 0134, “silicon layers 10L may be formed by an epitaxial deposition process in which a single crystalline silicon-germanium alloy material or a single crystalline silicon is deposited with epitaxial registry with underlying single crystalline semiconductor layers”
So Balakrishnan discloses the gate being formed by epitaxial growth, and Ju discloses the specifically well known understanding that epitaxially grown semiconductor material is formed in a single crystal orientation, and when an epitaxial process is carried out, the totality of the material is converted to single crystal semiconductor, since the entirety of the target material is subjected to high temperatures which result in the crystallization.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein the highly doped semiconductor layer within the gate length is a single crystalline layer, or along the gate length the highly doped semiconductor layer includes no more than three semiconductor grains”, as disclosed by Balakrishnan/Ju in the system of Kuroi, for the purpose of providing a materially more compatible gate structure with similar material to channel at a high concentration for high electron mobility performance capability. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 14, the prior art of Kuroi et al. disclose the semiconductor transistor in claim 12, wherein the semiconductor transistor is a PMOS transistor (Kuroi discloses in “FIG. 1 is a sectional view showing a PMOS transistor”, col. 10, line 55), the highly doped semiconductor layer is a highly doped silicon layer (Balakrishnan discloses in 0081, “The gate region 158 can include, but is not necessarily limited to, silicon (Si), silicon germanium (SiGe), or other semiconductor material.”), and the dopant activation concentration of the highly doped silicon layer is not less than 8 x1019/cm3 (Balakrishnan discloses in ¶ 0081, “The epitaxially grown gate region 158 can be in-situ doped during epitaxial growth processes, … a dopant concentration range may be e19/cm.sup.3 to e20/cm.sup.3, from 1e19/cm.sup.3 to 4e20/cm.sup.3 preferred.”).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Kuroi et al. (US 6,300,664) in view of Balakrishnan et al. (US 2019/0067280) in view of Cha et al. (US 2022/0285158) in view of Fukushima et al. (US 2013/0075824).
Regarding claim 17, the prior art of Kuroi et al. disclose the semiconductor transistor in claim 15, however Kuroi does not disclose, “wherein the semiconductor transistor is a transistor in a peripheral circuit of DRAM chip.”
Cha discloses in ¶ 0094, “The peripheral circuit region PERI may include an NMOS region NMOS and a PMOS region PMOS. The cell region CELL may include a DRAM cell array or a NAND memory cell string. In this embodiment, the cell region CELL may be a part of a DRAM cell array.”
Fukushima discloses wherein the peripheral circuit and the DRAM cell are portions of a chip, ¶ 0087, “Referring to FIG. 8, in the DRAM chip 36, a plurality of memory cell regions 37 with memory cell arrays formed therein are arranged in a row direction and a column direction. The peripheral circuit region 38 with a peripheral circuit constituted from an IO buffer and the like formed therein is disposed on the periphery of each memory cell region 37.”, and ¶ 0088, “Referring to FIGS. 9A and 9B, CMOS transistors that are the same as those in the second exemplary embodiment (refer to FIGS. 4A and 4B) are formed in the peripheral circuit region 38.”
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein the semiconductor transistor is a transistor in a peripheral circuit of DRAM chip”, as disclosed by Cha/Fukushima in the system of Kuroi, for the purpose of utilizing energy efficient CMOS transistors for use in a controller support role for the DRAM memory array. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Allowable Subject Matter
Claims 7-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 7, the prior art of Kuroi et al. disclose the method of claim 6, however Kuroi does not disclose the specific steps of method of forming gate on a gate dielectric layer,
“depositing an amorphous semiconductor layer over the gate dielectric layer;
annealing the amorphous semiconductor layer for recrystallization;
selectively growing the epitaxial doped semiconductor layer based on the recrystallized semiconductor layer; and
thermally annealing the epitaxial doped semiconductor layer.”
Claims 8 and 9 have been objected to, for the reason that they depend from claim 7.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eduardo A Rodela whose telephone number is (571)272-8797. The examiner can normally be reached M-F, 8:30-5:00pm ET.
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893
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