DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
RE: the rejection of claim(s) 1-8, 10-14 under 35 USC 112(b), Applicant’s arguments and/or amendments have been fully considered and resolve the issues of indefiniteness. Accordingly, the rejection of claim(s) 1-8, 10-14 has been withdrawn.
RE: the rejection of claim(s) 1-8, 10-14, 18-20 under 35 USC 103, Applicant’s arguments and/or amendments have been fully considered but are moot as further search and consideration prompted the new grounds of rejection presented herein.
RE: the rejection of claim(s) 15-17 under 35 USC 103, Applicant’s arguments and/or amendments are persuasive and have rendered claims 15-17 allowable over the prior art. Accordingly, the rejection of claims 15-17 under 35 USC 103 is withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 4-8, 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20220384325A1 (“Park”) in view of US20100096725A1 (“Shi”), further in view of US8643168B1 (“Wong”), further in view of US8723293B1 (“Jiang”).
RE: Claim 1, Park discloses A semiconductor package (package in FIG. 2), comprising:
a package substrate (100);
an interposer die (200) on the package substrate;
semiconductor chips (310, 320) on the interposer die,
the semiconductor chips electrically connected to the package substrate via the interposer die (interposer 200 may be used to facilitate the connection between the package substrate 100 and the semiconductor chips 310 and 320, [0024]; FIG. 6 shows 212a, 212b, 212c, 212d in 200 electrically connecting 310, 320 to 104 in 100, [0032], [0039]; Accordingly, 310, 320 are electrically connected to 100 via 200);
first connection bumps (392 in FIG. 2) electrically connecting the semiconductor chips to the interposer die;
second connection bumps (290 in FIG. 2) electrically connecting the interposer die to the package substrate; and
third connection bumps (190 in FIG. 2) disposed below the package substrate.
Park does not explicitly disclose:
wherein the interposer die includes spiral matching structures adjacent to upper portions of the second connection bumps, and
wherein the package substrate includes trace-shaped matching structures adjacent to lower portions of the second connection bumps, and
wherein an entirety of each of the spiral matching structures overlaps a corresponding one of the second connection bumps, in a plan view.
In the same field of endeavor, Shi discloses in FIG. 6:
an interposer die (140) includes a spiral matching structure (166; spiral trace addresses impedance mismatches, [0063]) adjacent to an upper portion of a second connection bump (170).
FIG. 6 shows a via 157 connecting the spiral trace 166 to the pad 167 in direct contact with solder ball 170, [0059], [0062].
Shi further discloses in FIG. 9:
a die (120) includes spiral matching structures (124a, 124b, 124c, [0062]) adjacent to upper portions of the second connection bumps (130a, 130b, 130c, [0080]).
Shi further discloses The spiral trace acts as an inductor that can compensate for large capacitances in the package, thereby maintaining a desired characteristic impedance. The spiral takes up very little area, and its ends (input and output) are near one another. During the design of the package, the characteristics of the spiral are chosen so as to provide a desired inductance, thereby providing a desired impedance of the package as a whole, [0016].
Shi further discloses the spiral trace or inductor is disposed near an IC die of the package, to act as an inductor to compensate for the capacitive loading (Ci) of the die by cooperating with the capacitance to establish a desired characteristic impedance, [0047].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide spiral matching structures adjacent to upper portions of second connection bumps 290 by using a via connecting a spiral matching structure to each pad 220 as taught by Shi in order to compensate for capacitive loading and establish a desired characteristic impedance.
In the same field of endeavor, Wong discloses in FIGs. 7-8:
a package substrate (705; Col. 4, lines 60-67) includes trace-shaped matching structures (each load-matched trace section 710 of 700, Col. 4, line 67) adjacent to lowers portions of second connection bumps (Note: the term “adjacent” is not defined in the instant specification; The term “adjacent” has been defined as “not distant : nearby,” see definition 1b by Merriam-Webster’s dictionary; Wong discloses Each narrow trace section 315 connects to a corresponding pad 320. As known in the BGA package arts, a solder resist layer 325 includes an opening 330 above each pad 320 to receive a solder bump from a flip-chip die (discussed with regard to FIG. 1), Col. 3, lines 20-25, see opening 330 labeled in FIG. 3; In FIG. 7, the opening would also receive a solder bump; As FIG. 7 shows 700 is adjacent to a lower portion the opening that receives a solder bump, 700 would also be adjacent to a lower portion of the solder bump when the solder bump is received by the opening).
FIG. 7 shows a via 360 connecting the pad 320 to the load-matched trace section 710 of 700.
Additionally, Wong discloses 705 is a BGA substrate, Col. 4, lines 60-65.FIG. 7 shows the load-matched trace section 700, 710 adjacent to a top surface of the BGA substrate 705.
FIG. 2 shows the top surface of the BGA substrate 105 is adjacent to solder bumps 115, Col. 2, lines 40-45.
Accordingly, Wong discloses each load-matched trace section 710 would be adjacent to a solder bump.
Wong further discloses Each trace 700 includes a load-matched trace section 710 with enhanced inductance to balance the capacitive load for pad 320 (as well as associated circuitry on the die), Col. 4 line 60 to Col. 5, line 5.
Wong further discloses A tapered section 735 softens the transition between sections 710 and 720 and reduces reflections accordingly, Col. 5, lines 19-25.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide trace-shaped matching structures with tapered sections adjacent to lower portions of second connection bumps 290 by using a via connecting a trace-shaped matching structure to each pad 104 as taught by Wong in order to balance capacitive load and reduce reflections.
In the same field of endeavor, Jiang discloses in FIG. 3:
an entirety of a spiral matching structure (54; With the compensation inductor 54 implemented as a spiral underneath a bump pad 20, the compensation inductor 54 consumes little on-die space, Col. 4, lines 45-48; the compensation inductor 54 is configured as a spiral inductor, Col. 4, lines 28-30) overlaps a corresponding one of a second connection bump (bump 12, Col. 4, lines 30-32), in a plan view (FIG. 3 shows an entirety of spiral inductor 54 would overlap bump 12 in a top perspective view, and shows 54 would also overlap bump 12 in a plan view).
Jiang further teaches Embodiments described below provide a network for compensating die pin capacitance in a die-package system to reduce system return loss and insertion loss that is effective over a broad range of frequencies, Col. 3, lines 10-15.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify each spiral matching structure so that an entirety of each of the spiral matching structures overlaps a corresponding one of the second connection bumps, in a plan view as taught by Jiang in order to reduce system return loss and insertion loss over a broad range of frequencies as further taught by Jiang.
RE: Claim 2, Park in view of Shi, Wong, Jiang discloses The semiconductor package of claim 1, wherein the spiral matching structures and the trace-shaped matching structures are configured to compensate for mismatching of impedance caused by the second connection bumps (Park teaches 290 are solder bumps, [0113]; Shi teaches the capacitance of the solder ball generally has a lower limit. This leads to the package structure having a low impedance caused by the high capacitance of the solder ball, [0019]-[0023]; Shi further teaches a spiral trace configured to address capacitance of the solder ball and any resulting impedance mismatches between the package and the PCB, [0057]; The spiral trace acts as an inductor that can compensate for large capacitances in the package, [0016]; Accordingly, as modified, the spiral matching structures are configured to compensate for mismatching of impedance caused by the second connection bumps;
Further, Wong teaches the pads on ball grid array (BGA) substrate 105 in conjunction with associated circuitry on die 110 have a relatively-high capacitance. Such capacitance represents a low-impedance load to a high-speed signal. In contrast, the traces on circuit board 120 have a relatively-high impedance. To address the impedance mismatch, the BGA substrate traces are modified such that pads on the BGA substrate couple to low-impedance matching trace sections in the BGA substrate that are configured to have a relatively-high inductance. This inductance in combination with the capacitance of the pads and associated circuitry on the die present an impedance-matched load to the signals coming from the circuit board trace, Col. 2, lines 50-62; Shi teaches the solder balls have a high capacitance, [0019]-[0023]; As Wong teaches the traces 710 are impedance matched and they would be electrically connected with the solder bumps 290, they would be configured to compensate for mismatch of impedance caused by the solder bumps 290).
RE: Claim 4, Park in view of Shi, Wong, Jiang discloses The semiconductor package of claim 1,
wherein the interposer die further includes lower pads (From Park FIGs. 2-3: 220; From Shi FIG. 6: 167) in contact with the upper portions of the second connection bumps, and connection vias (From Shi FIG. 6: micro-vias 157, [0059]; Shi discloses embodiments may include any suitable number and arrangement of dielectric layers, conductive layers, vias, micro-vias, or the like, [0059]) connecting the lower pads to the spiral matching structures (FIG. 6 Shi shows via 157 connecting lower pad 167 to spiral matching structure 166; Accordingly as modified, Shi’s micro-vias would connect Park’s lower pads 220 to Shi’s spiral matching structures 166).
RE: Claim 5, Park in view of Shi, Wong, Jiang discloses The semiconductor package of claim 1, wherein each of the trace-shaped matching structures has one end electrically connected to the second connection bumps (FIGs. 7-8 Wong shows 710 having one left end electrically connected to a pad 320; Accordingly, as modified, each of Wong’s trace-shaped matching structures 710 would have one end electrically connected to Park’s pads 104 in FIG. 2 which is electrically connected to Park’s second connection bumps 290).
RE: Claim 6, Park in view of Shi, Wong, Jiang discloses The semiconductor package of claim 5, wherein the package substrate further includes upper pads (FIG. 2 Park 104) in contact with the lower portions of the second connection bumps (FIG. 2 Park shows upper pads 104 in contact with the lower portions of the second connection bumps 290), and connection vias (From FIG. 7 Wong: plurality of vias 360, Col. 4, line 24) connecting the upper pads to the one end of each of the trace-shaped matching structures (FIGs. 7-8 Wong shows a via 360 connecting the upper pad 320 to the one left end of the trace-shaped matching structure 710; Accordingly, as modified, Wong’s connection vias would connect Park’s upper pads 104 to the one end of each of Wong’s trace-shaped matching structures).
RE: Claim 7, Park in view of Shi, Wong, Jiang discloses The semiconductor package of claim 5, wherein the package substrate further includes upper pads (FIG. 2 Park 104) in contact with the one end of each of the trace-shaped matching structures and the lower portions of the second connection bumps (FIGs. 3-4 show matched narrow trace sections 315 in direct contact with pads 320; see Col. 4, lines 1-5; Col. 3, lines 20-25; FIGs. 7-8 Wong shows pad 320 in indirect contact or electrical contact or thermal contact with the one left end of 710; Accordingly as modified, Park’s upper pads 104 would be in indirect contact with the one end of each of Wong’s trace-shaped matching structures 710; FIG. 2 Park shows pads 104 in contact with each of the second connection bumps 290; Note the reference US20180335585A1 discloses One layer “over”, “spanning”, or “on” another layer or bonded “to” or in “contact” with another layer may be directly in contact with the other layer or may have one or more intervening layers, [0034]; accordingly, under a broad reasonable interpretation, “in contact” means one or more intervening layers are present).
RE: Claim 8, Park in view of Shi, Wong, Jiang discloses The semiconductor package of claim 5, wherein the package substrate further includes a wiring circuit (FIGs. 7-8 Wong: tapered section 735, Col. 5, line 20) in contact with another end of each of the trace-shaped matching structures (FIGs. 7-8 Wong shows a tapered section 735 in contact with the other right end of the trace-shaped matching structure 710; Accordingly as modified Wong’s tapered section 735 would be in contact with the other end of each of Wong’s trace-shaped matching structures 710; The combination of tapered sections is considered to correspond to the claimed wiring circuit).
RE: Claim 11, Park in view of Shi, Wong, Jiang discloses The semiconductor package of claim 1, wherein each of the second connection bumps has a second width greater than a first width of each of the first connection bumps (Park FIG. 2 shows each of the second connection bumps 290 has a second width greater than a first width of each of the first connection bumps 392).
RE: Claim 12, Park in view of Shi, Wong, Jiang discloses The semiconductor package of claim 11, wherein each of the third connection bumps has a third width greater than the second width of each of the second connection bumps (Park FIG. 2 shows each of the third connection bumps 190 has a third width greater than the second width of each of the second connection bumps 290).
RE: Claim 13, Park in view of Shi, Wong, Jiang discloses The semiconductor package of claim 1, wherein the semiconductor chips include a first semiconductor chip (Park FIG. 2: 310) and a second semiconductor chip (Park FIG. 2: 320), the first semiconductor chip and the second semiconductor chip being side by side on the interposer die (Park FIG. 2 shows 310, 320 side by side on the interposer die 200), and wherein the interposer die further includes an upper connection circuit (Park FIG. 6: 212d, [0039]) electrically connecting the first semiconductor chip to the second semiconductor chip (upper right region of FIG. 6 shows layer 212d electrically connecting 310 to 320).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Shi, Wong, Jiang as applied to claim 1, further in view of US 20050205295 A1 (“Tsuk”).
RE: Claim 3, Park in view of Shi, Wong, Jiang does not explicitly disclose:
The semiconductor package of claim 1, wherein the spiral matching structures and the trace-shaped matching structures are configured to reduce signal delay.
However, Shi discloses During the design of the package, the characteristics of the spiral are chosen so as to provide a desired inductance. This inductance provides a desired impedance of the package as a whole, [0047].
Shi further discloses spiral trace may address impedance mismatches between the substrate 140 and the PCB 180, as discussed above in relation to FIGS. 1-5, [0063].
Wong teaches low-impedance matching trace sections in the BGA substrate that are configured to have a relatively-high inductance. This inductance in combination with the capacitance of the pads and associated circuitry on the die present an impedance-matched load to the signals, Col. 2, lines 55-62.
In the same field of endeavor, Tsuk teaches Noting that impedance is the square root of the ratio of inductance per unit length to capacitance per unit length, and that vias tend to have very large capacitances due to the effects of pads on the vias, and nearby reference planes, a desirable impedance may be achieved by either reducing the capacitance, or as shown and described here, by increasing the inductance. Thus, by increasing the inductance the impedance in the loop(s) will better match and thus reduce signal delays, [0024].
Accordingly, as the spiral matching structures and the trace-shaped matching structures introduce inductance and compensate for impedance mismatching, they would reduce signal delay.
Alternatively, it would have been obvious to one of ordinary skill in the art to increase inductance in the spiral matching structures and the trace-shaped matching as taught by Tsuk in order to better match impedance and reduce signal delay.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Shi, Wong, Jiang as applied to claim 1, further in view of US 20220359320 A1 (“Jeng”).
RE: Claim 10 Park in view of Shi, Wong, Jiang discloses The semiconductor package of claim 1, wherein the package substrate further includes a wiring circuit (Wong FIG. 8: 735), and wherein the trace-shaped matching structures (From Wong FIG. 8: 710) have a line width smaller than a line width of the wiring circuit (FIG. 8 shows the trace-shaped matching structure 710 has a line width smaller than a line width of the wiring circuit 735; Accordingly as modified, the trace-shaped matching structures have a line width smaller than a line width of the wiring circuit).
Park in view of Shi, Wong, Jiang does not explicitly disclose:
the wiring circuit electrically connecting the second connection bumps to the third connection bumps.
However, in the same field of endeavor, Jeng discloses in FIG. 1:
102 is a package substrate, [0017].
Each conductive bump 136 may be electrically connected to one of the conductive features 106 of the package substrate 102. The conductive bumps 136 enable electrical connection between the package structure and an external device (not shown). The conductive bumps 136 may be or include solder bumps such as tin-containing solder bumps, [0051].
Jeng further discloses The conductive features 106 may include conductive lines, conductive vias, and/or conductive pads, [0018].
Jeng further discloses Each conductive element 108 (such as a conductive pillar) may be exposed at or protruding from the topmost surface of the insulating layers 104, and may be electrically connected to one of the conductive features 106, [0026].
Jeng further discloses the interposer substrate 110 (integrated with the semiconductor devices 120 and 128) is bonded onto the conductive elements 108 through conductive structures 116. The conductive structures 116 may include solder bumps, solder balls, [0046].
FIG. 1G shows the bumps 116 in direct contact with the conductive elements 108.
Accordingly, Jeng teaches the conductive features 106 electrically connect bumps 116 on one side of the package substate to bumps 136 on another side of the package substrate 102.
Further, Wong teaches the traces 700 include a load-matched trace section 710, Col. 4, line 67.
FIGs. 7-8 show the load-matched trace section 710 and the tapered section 735 are part of the same trace 700.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the traces including the trace-shaped matching structures and tapered sections so that they electrically connect the second connection bumps 290 to the third connection bumps 190 in FIG. 2 Park as taught by Jeng in order to enable electrical connection and/or communication between the package substrate 100 and an external device.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Shi, Wong, Jiang as applied to claim 1, further in view of US20130176764A1 (“Lee”).
RE: Claim 14, Park in view of Shi, Wong, Jiang discloses The semiconductor package of claim 1, wherein the semiconductor chips are vertically stacked on the interposer die (FIG. 2 Park shows 310, 320 are vertically stacked on 200), and
wherein the semiconductor chips include a memory circuit (semiconductor chip 320 may be a memory semiconductor chip. For example, the second semiconductor chip 320 may be a volatile memory, e.g., a DRAM (Dynamic Random Access Memory) or a SRAM (Static Random Access Memory), or may be a non-volatile memory, e.g., a flash memory, a PRAM (Phase-change Random Access Memory), a MRAM (Magnetoresistive Random Access Memory), a FeRAM (Ferroelectric Random Access Memory) or a RRAM (Resistive Random Access Memory), [0061]; semiconductor chip 320 may be a stack memory, e.g., a high bandwidth memory (HBM). Such a stack memory may have a form in which a plurality of ICs are stacked. The stacked ICs may be electrically connected to each other through a TSV (Through Silicon Via) or the like, [0062]; Accordingly 320 would include a memory circuit).
Park in view of Shi, Wong, Jiang does not explicitly disclose:
wherein the interposer die includes a logic circuit.
In the same field of endeavor, Lee discloses in FIG. 2:
The interposer 20 may correspond to a logic die as a chip including logic circuits for enabling communication between an external circuit (not illustrated) of the semiconductor apparatus and the controller 30, between the external circuit and the memories 40 and 50, and between the controller 30 and the memories 40 and 50, and may include signal lines between the external circuit and the controller 30, between the external circuit and the memories 40 and 50, and between the controller 30 and the memories 40 and 50, [0020].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the interposer 200 to include logic circuits as taught by Lee in order to enable communication between an external circuit and memory chips 320.
Claim(s) 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Shi, further in view of Wong, further in view of Jiang.
RE: Claim 18, Park discloses A semiconductor package (package in FIG. 2), comprising:
a package substrate (100);
an interposer die (200) on the package substrate;
semiconductor chips (310,320) on the interposer die;
first connection bumps (392 in FIG. 2) electrically connecting the semiconductor chips to the interposer die; and
second connection bumps (290 in FIG. 2) electrically connecting the package substrate to the interposer die.
Park does not explicitly disclose:
the package substrate includes first matching structures and a wiring circuit electrically connected to the first matching structures;
the interposer die including second matching structures;
the second connection bumps electrically connect the first matching structures of the package substrate to the second matching structures of the interposer die;
wherein the first matching structures and the second matching structures have different shapes to compensate for mismatching of impedance caused by the second connection bumps, and
wherein an entirety of each of the second matching structures overlaps a corresponding one of the second connection bumps, in a plan view.
In the same field of endeavor, Shi discloses in FIG. 6:
an interposer die (140) including a second matching structure (166; spiral trace addresses impedance mismatches, [0063]).
FIG. 6 shows a via 157 connecting the spiral trace 166 to the pad 167 in direct contact with solder ball 170, [0059], [0062].
Shi further discloses in FIG. 9:
a die (120) including second matching structures (124a, 124b, 124c, [0062]).
Shi further discloses The spiral trace acts as an inductor that can compensate for large capacitances in the package, thereby maintaining a desired characteristic impedance. The spiral takes up very little area, and its ends (input and output) are near one another. During the design of the package, the characteristics of the spiral are chosen so as to provide a desired inductance, thereby providing a desired impedance of the package as a whole, [0016].
Shi further discloses the spiral trace or inductor is disposed near an IC die of the package, to act as an inductor to compensate for the capacitive loading (Ci) of the die by cooperating with the capacitance to establish a desired characteristic impedance, [0047].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide in the interposer die 200 spiral matching structures (corresponding to the claimed second matching structures) adjacent to a lower surface of the interposer die 200 by using a via connecting a spiral matching structure to each pad 220 as taught by Shi in order to compensate for capacitive loading and establish a desired characteristic impedance.
In the same field of endeavor, Wong discloses in FIGs. 7-8:
a package substrate (705; Col. 4, lines 60-67) includes first matching structures (each load-matched trace section 710 of 700, Col. 4, line 67) and a wiring circuit (735, Col. 5, lines 19-25) electrically connected to the first matching structures (FIGs. 7-8 shows 710 electrically connected to 735).
FIGs. 7-8 show the trace 700, 710 electrically connected to the pad 320.
Wong further discloses Each trace 700 includes a load-matched trace section 710 with enhanced inductance to balance the capacitive load for pad 320 (as well as associated circuitry on the die), Col. 4 line 60 to Col. 5, line 5.
Wong further discloses A tapered section 735 softens the transition between sections 710 and 720 and reduces reflections accordingly, Col. 5, lines 19-25.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide in the package substrate 100 trace-shaped matching structures (corresponding to the claimed first matching structures) with tapered sections adjacent to an upper surface of the package substrate by using a via connecting a trace-shaped matching structure to each pad 104 as taught by Wong in order to balance capacitive load and reduce reflections. Under a broad reasonable interpretation, the combination of tapered sections is considered to correspond to the claimed wiring circuit.
As modified, the trace-shaped matching structures would be electrically connected to the pads 104 of the second connection bumps 290, and the spiral matching structures would be electrically connected to the pads 220 of the second connection bumps 290. Accordingly, as modified, the second connection bumps 290 would electrically connect the spiral matching structures of the interposer die 200 to the trace-shaped matching structures of the package substrate 100.
Further, Shi discloses 166 is a spiral trace, [0060].
Shi discloses a spiral trace 49 may include a substantially circular spiral such as that shown in FIG. 3A, and/or it may include a polygonal spiral such as those shown in FIGS. 3B-3D or the like, i.e., octagonal (FIG. 3B), square (FIG. 3C), or hexagonal (FIG. 3D). Using current substrate preparation techniques, polygonal spirals such as those shown in FIGS. 3B-3D may be easier to manufacture, [0043].
Shi further discloses spiral trace 124 may include a polygonal spiral such as those shown in FIGS. 7A-7B or the like, i.e., square (FIG. 7A), or hexagonal (FIG. 7B), and/or it may include a substantially circular spiral such as that shown in FIG. 7C. Using semiconductor manufacturing processes, polygonal spirals such as those shown in FIGS. 7A-7B may be easier to manufacture, [0076].
Accordingly, the spiral trace would have a spiral shape.
Further, Park teaches 290 are solder bumps, [0113].
Shi teaches the capacitance of the solder ball generally has a lower limit. This leads to the package structure having a low impedance caused by the high capacitance of the solder ball, [0019]-[0023].
Shi further teaches a spiral trace configured to address capacitance of the solder ball and any resulting impedance mismatches between the package and the PCB, [0057]. The spiral trace acts as an inductor that can compensate for large capacitances in the package, [0016].
Accordingly, as modified, the spiral matching structures would compensate for mismatching of impedance caused by the second connection bumps 290 in Park.
Wong FIGs. 7-8 show the matching structures 710 has a linear shape, not a spiral shape.
Wong teaches the pads on ball grid array (BGA) substrate 105 in conjunction with associated circuitry on die 110 have a relatively-high capacitance. Such capacitance represents a low-impedance load to a high-speed signal. In contrast, the traces on circuit board 120 have a relatively-high impedance. To address the impedance mismatch, the BGA substrate traces are modified such that pads on the BGA substrate couple to low-impedance matching trace sections in the BGA substrate that are configured to have a relatively-high inductance. This inductance in combination with the capacitance of the pads and associated circuitry on the die present an impedance-matched load to the signals coming from the circuit board trace, Col. 2, lines 50-62.
Shi teaches the solder balls have a high capacitance, [0019]-[0023].
As Wong teaches the traces 710 are impedance matched and would be electrically connected with the solder bumps 290, the traces 710 would compensate for mismatch of impedance caused by Park’s solder bumps 290.
As a result, Shi’s spiral shaped matching structures and Wong’s linear shaped matching structures have different shapes to compensate for mismatching of impedance caused by Park’s second connection bumps 290.
In the same field of endeavor, Jiang discloses in FIG. 3:
an entirety of a second matching structure (54; With the compensation inductor 54 implemented as a spiral underneath a bump pad 20, the compensation inductor 54 consumes little on-die space, Col. 4, lines 45-48; the compensation inductor 54 is configured as a spiral inductor, Col. 4, lines 28-30) overlaps a corresponding one of the second connection bump (bump 12, Col. 4, lines 30-32), in a plan view (FIG. 3 shows an entirety of spiral inductor 54 would overlap bump 12 in a top perspective view, and shows 54 would also overlap bump 12 in a plan view).
Jiang further teaches Embodiments described below provide a network for compensating die pin capacitance in a die-package system to reduce system return loss and insertion loss that is effective over a broad range of frequencies, Col. 3, lines 10-15.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify each spiral matching structure so that an entirety of each of the spiral matching structures overlaps a corresponding one of the second connection bumps, in a plan view as taught by Jiang in order to reduce system return loss and insertion loss over a broad range of frequencies as further taught by Jiang.
RE: Claim 19, Park in view of Shi, Wong, Jiang discloses The semiconductor package of claim 18, wherein each of the first matching structures has a trace shape having a line width smaller than a line width of the wiring circuit (Wong FIGs. 7-8 show each of the first matching structures 710 has a trace shape having a line width smaller than a line width of the wiring circuit 735; Accordingly as modified, each of the first matching structures has a trace shape having a line width smaller than a line width of the wiring circuit).
RE: Claim 20, Park in view of Shi, Wong, Jiang discloses The semiconductor package of claim 18, wherein each of the second matching structures has a single layer or a multilayer spiral shape (Shi FIG. 6 shows the second matching structure 166 having a single layer spiral shape; Shi FIG. 9 shows each of the second matching structures 124a, 124b, 124c having a single layer spiral shape; Accordingly as modified, each of the second matching structures would have a single layer spiral shape).
Allowable Subject Matter
Claims 15-17 are allowable.
The following is a statement of reasons for the indication of allowable subject matter: Further search identified Jiang, US20100237462A1, US9219041B2, US20060227522A1, US20150279545A1. These references, as well as the prior art of record fails to disclose “wherein a line width of each of the spiral matching structures is less than or equal to a line width of each of the trace-shaped matching structures, and wherein a line width of each of the trace-shaped matching structures is smaller than a line width of the wiring circuit” as required by claim 15.
Applicant’s arguments were persuasive in that without any teaching in the cited art that trace-shaped matching structures, spiral matching structures, and a wiring circuit interact - let alone that their relative dimensions impact performance - the only source or blueprint for this specific combination is the applicant's own disclosure. It is well-established that an examiner cannot use the applicant's specification as a guide to cherry-pick individual dimensions from disparate references to reconstruct the claimed invention.
Further, Jiang in particular does not disclose a trace-shaped matching structure in combination with a wiring circuit. Accordingly, Jiang does not disclose “wherein a line width of each of the trace-shaped matching structures is smaller than a line width of the wiring circuit.” In Jiang FIG. 3, the spiral inductor 54 and a transmission line 44 are shown with different widths. Jiang is silent as to dimensions and Jiang does not disclose the drawings are to scale. As FIG. 3 shows merely a portion of elements in FIG. 1A, the sizes shown are not relied upon to show different proportions, see MPEP 2125. Accordingly, Jiang does not disclose “wherein a line width of each of the spiral matching structures is less than or equal to a line width of each of the trace-shaped matching structures.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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