DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Species 8 in the reply filed on May 11, 2026 is acknowledged.
However, claims 7, 8, 17, and 18 are hereby withdrawn, due to the following reasons. Claims 7 and 8 recite inner/internal spacers which are not included or disclosed with elected species 8; claims 17 and 18 recite plural fin structures which are not included or disclosed with elected species 8.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The references cited within the IDS document have been considered.
IDS document date: January 25, 2024.
Specification (Title)
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 9-13, 16, 19, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang et al. (US 2021/0091211 A1, hereinafter referred to as ‘Kang’).
As to claim 1, Kang teaches a semiconductor device comprising:
a substrate (100) having a first conductivity type;
a well region (104) having a second conductivity type in the substrate;
an impurity implantation region (106) having the first conductivity type in the well region;
an element separation pattern (ST) in the substrate;
a first fin pattern (see area under CTa) defined by the element separation pattern in the impurity implantation region;
a second fin pattern (see area under CTb) defined by the element separation pattern in the well region; and
a third fin pattern (see area under CTc) defined by the element separation pattern in the substrate,
wherein the first fin pattern is a single fin pattern, and
an entirety of a lower boundary of the impurity implantation region (106) is in contact with the well region (104). See figures 18 and 23A.
As to claim 2, Kang teaches a fin structure including sacrificial patterns (110) and semiconductor patterns (112) alternately stacked on the first fin pattern; and
a contact (CT) connected to one or more of the semiconductor patterns. See figures 18 and 23A.
As to claim 3, Kang teaches an entirety of an upper boundary of the impurity implantation region (106) is in contact with the fin structure. See figures 18 and 23A.
As to claim 4, Kang teaches a gate structure (GS) on the fin structure,
wherein the contact (CT) is on a side surface of the gate structure. See figures 18 and 23A.
As to claim 5, Kang teaches first semiconductor patterns (AFb) stacked on the second fin pattern;
a first gate structure (GS) on the first semiconductor patterns on the second fin pattern;
a first source/drain pattern (i.e. connection pattern, 120) connected to the first semiconductor patterns and having the second conductivity type (para. 0056), on a side surface (see also fig. 23A) of the first gate structure;
second semiconductor patterns (AFc) stacked on the third fin pattern;
a second gate structure (GS) on the second semiconductor patterns on the third fin pattern; and
a second source/drain pattern (i.e. connection pattern, 122) connected to the second semiconductor patterns and having the first conductivity type (para. 0057), on a side surface (see also fig. 23A) of the second gate structure.
As to claim 6, Kang teaches each of the first gate structure and the second gate structure includes a gate electrode (GE), a gate insulating film (GI), and a gate spacer (GSP). See figures 18 and 23A.
As to claim 9, Kang teaches first sacrificial patterns and first semiconductor patterns (AF) alternately stacked on the second fin pattern; and
a first contact (CT) connected to one or more of the first semiconductor patterns. See figures 18 and 23A.
As to claim 10, Kang teaches second sacrificial patterns and second semiconductor patterns (AF) alternately stacked on the third fin pattern; and
a second contact (CT) connected to one or more of the second semiconductor patterns. See figures 18 and 23A.
As to claim 11, Kang teaches second semiconductor patterns (AF) stacked on the third fin pattern;
a gate structure (GS) on the second semiconductor patterns on the third fin pattern;
a source/drain pattern (122) connected to the second semiconductor patterns and having the first conductivity type, on a side surface of the gate structure; and
a second contact (CT) connected to the source/drain pattern. See figures 18 and 23A.
As to claim 12, Kang teaches first semiconductor patterns (AF) stacked on the second fin pattern;
a gate structure (GS) on the first semiconductor patterns on the second fin pattern;
a source/drain pattern (120) connected to the first semiconductor patterns and having the second conductivity type, on a side surface of the gate structure;
a first contact (CT) connected to the source/drain pattern;
first sacrificial patterns and second semiconductor patterns (AF) alternately stacked on the third fin pattern; and
a second contact (CT) connected to one or more of the second semiconductor patterns. See figures 18 and 23A.
As to claim 13, Kang teaches a semiconductor device comprising:
a substrate (100) having a first conductivity type;
a well region (104) having a second conductivity type in the substrate;
an impurity implantation region (106) having the first conductivity type in the well region; and
a first fin structure (see area under CTa) including first sacrificial patterns and first semiconductor patterns (AF, 110 and 112) alternately stacked on the impurity implantation region,
wherein an entirety of an upper boundary of the impurity implantation region (106) is in contact with the first fin structure. See figures 18 and 23A.
As to claim 16, Kang teaches an entirety of a lower boundary of the impurity implantation region (106) is in contact with the well region (104). See figures 18 and 23A.
As to claim 19, Kang teaches a semiconductor device comprising:
a substrate (100) having a first conductivity type;
a well region (104) having a second conductivity type in the substrate;
an impurity implantation region (106) having the first conductivity type in the well region;
an element separation pattern (ST) in the substrate;
a first fin pattern (see area under CTa) defined by the element separation pattern in the impurity implantation region (106);
a second fin pattern (see area under CTb) defined by the element separation pattern in the well region (104);
a third fin pattern (see area under CTc) defined by the element separation pattern in the substrate (100);
a first fin structure including first sacrificial patterns and first semiconductor patterns (AF) alternately stacked on the first fin pattern in a first direction perpendicular to an upper surface of the substrate;
a second fin structure including second semiconductor patterns (AF) spaced apart from each other in the first direction on the second fin pattern; and
a third fin structure including third semiconductor patterns (AF) spaced apart from each other in the first direction on the third fin pattern,
wherein the first fin pattern is a single fin pattern and the first fin structure is a single fin structure, and in a second direction parallel to the upper surface of the substrate, a width of the first fin structure is the same as a width of the impurity implantation region. See figures 18 and 23A.
As to claim 20, Kang teaches wherein, in a third direction parallel to the upper surface of the substrate and intersecting the second direction, a length of the first fin structure is the same as a length of the impurity implantation region (106). See figures 17, 18, and 23A.
Allowable Subject Matter
Claims 14 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claim 14, the prior art of record does not teach or suggest the disclosed invention regarding a plurality of second fin structures including second semiconductor patterns stacked on the well region and arranged in a first direction; and
a gate structure extending in the first direction on the plurality of second fin structures,
wherein in the first direction, a width of the first fin structure is greater than a width of the second fin structure.
As to claim 15, the prior art of record does not teach or suggest the disclosed invention regarding a a plurality of second fin structures including second semiconductor patterns stacked on the substrate and arranged in a first direction; and
a gate structure extending in the first direction on the plurality of second fin structures,
wherein in the first direction, a width of the first fin structure is greater than a width of the second fin structure.
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: see the attached form PTO-892 for pertinent cited art.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Scott B. Geyer (telephone: 571-272-1958). The examiner can normally be reached on Monday to Friday, 10AM - 4PM (ET). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at: http://www.uspto.gov/interviewpractice.
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/SCOTT B GEYER/ Primary Examiner, Art Unit 2812
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