DETAILED ACTION
This action is responsive to the election received on 05/13/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A (Figures 1 and 3B) in the reply filed on 05/13/2026 is acknowledged. Claim(s) 9-11 and 19-20 is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Claim 9 (and claims 10-11 by their dependency) requires “an upper semiconductor pattern surrounds four side surfaces of the gate electrode” in line 5 of the claim. Claim 19 (and claim 20 by its dependency) requires “channel regions . . . arranged on both side surfaces of the gate lines in the first horizontal direction” in lines 6-8 of the claim. These limitations are interpreted by the examiner as reading on the non-elected species B (Figures 4A and 4B) wherein an upper semiconductor pattern (#130-2) surrounds four side surfaces of the gate electrode (#120-2), as described in [0057], and channel regions (#132-1 and #132-2) are arranged on both sides of the gate line (120a) in the horizontal direction (x-direction). This is not observed to be supported by elected species A (Figures 1 and 3B) wherein the gate electrode (word line, #120) is arranged on opposing sides of the channel region (#132) which is opposite that of species B.
Claim Objections
Claim(s) 1-8 and 12-15 is/are objected to because of the following informalities where proposed corrections are bolded and underlined:
Claim 1, lines 9-10, “ferroelectric capacitor (FeCap) structures over the semiconductor patterns in [[the]] a vertical direction” as this is the first recitation of a vertical direction;
Claim 2, line 2, “has a quadrangular shape, and the ferroelectric layer covering”, where there appears to be several additional spaces between the words ‘and’ and ‘the’;
Claim 12, lines 14, “and[[ n]] horizontal extensions extending from a side surface” where there appears to be an extra ‘n’ within the line that is either a typo or intended to represent an integer number of horizontal extensions which has not been defined by the claim.
The balance of claims are objected to at least for their dependencies. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-8 and 12-18 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Several claims in the instant application recite a singular element after previously reciting a plurality of said elements but never specifying if the singular one of such elements is part of the original plurality or is intended to be separate from the plurality. This results in an issue of unclear antecedent basis as it is unclear if the singular element is part of the previously recited plurality of elements or if the singular element is intended to represent a new element separate from the group. The examiner has several instances in the following list:
Claim 1, line 5, “word lines disposed over the bit line” while the previous recitation in claim 1, line 2 was for “bit lines extending in a first horizontal direction”;
Claim 3, line 1, “a horizontal extension” while the previous recitation in claim 1, lines 12-14, was for “a first electrode comprising . . . at least two horizontal extensions extending from side surfaces of the body portion”;
Claim 5, line 1, “the second electrode” while the previous recitation in claim 1, line 17, was for “second electrodes covering the ferroelectric layer”;
Claim 8, lines 1-2, “both sides of the semiconductor pattern” while the previous recitation in claim 1, line 7, was for “semiconductor patterns”;
Claim 14, line 1, “the second electrode” while the previous recitation in claim 12, line 18, was for “a plurality of second electrodes covering the ferroelectric layer”;
Claim 16, line 6, “at least one transistor (TR) on the bit line” while the previous recitation in claim 16, line 4, was for “bit lines extending in a first horizontal direction”;
Claim 17, line 4, “word lines disposed over the bit line” while the previous recitation in claim 16, line 4, was for “bit lines extending in a first horizontal direction”;
Claim 18, line 1, “a horizontal extension” while the previous recitation in claim 16, lines 9-11, was for “a first electrode comprising . . . a plurality of horizontal extensions extending in the first direction from a side surface of the body portion”;
Claim 18, lines 3-4, “the second electrode” while the previous recitation in claim 16, line 18, was for “a plurality of second electrodes covering the ferroelectric layer”.
For the purposes of this examination, all instances of a singular element recitation following a recitation of a plurality of the element will be interpreted that the singular element may or may not be part of the plurality and still read on the claim.
Regarding claims 2, 4, 5, 13, and 14, the phrase “ring-like shape” as it is used in each of these claims is a relative term. It is unclear what is meant by “ring-like” and if/how this is different than the corresponding element having a ring shape. It is unclear if the use of the phrase “ring-like” is intended to encompass shapes which are not complete rings and are instead simply close to being a complete ring, and if that is the case then it is unclear how much of the ring needs to be present in order to be considered ring-like.
Regarding claims 6 and 14, the phrase “tube-like” as it is used in each of these claims is a relative term. It is unclear what is meant by “tube-like” and if/how this is different than the corresponding element having a tube shape. It is unclear if the use of the phrase “tube-like” is intended to encompass shapes which are not complete tubes and are instead simply close to being a complete tube, and if that is the case then it is unclear how much of the tube needs to be present in order to be considered tube-like.
Several claims in the instant application recite “the ferroelectric layer of the horizontal extension” (see for example claims 4, 13, and claim 18) while claims on which they depend (claims 1, 12, and 16, respectively) recite “a ferroelectric layer covering . . . the horizontal extensions”. It is unclear if the applicant is referring to the portions of the ferroelectric layer on a respective horizontal extension or if the horizontal extensions further include an additional ferroelectric layer which is part of the horizontal extension(s) of the first electrode.
Claim 6 recites the limitation “the quadrangular tube-like portion of the second electrode” in lines 1-2, lines 2-3, and line 4. Claim 5 has previously recited “the second electrode has a shape of a quadrangular tube” in the first two lines of the claim. It is unclear if the quadrangular tube-like portion of the second electrode is intended to refer to the entirety of the quadrangular tube shaped second electrode or is only referring to a portion of the quadrangular tube structure of the second electrode.
Each of the claims identified above is therefore rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention. The balance of claims are rejected under 35 U.S.C. 112(b) at least for their dependencies.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8 and 12-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2026/0129865 A1; Yin et al.; 05/2026; (“Yin”) in view of US 2024/0008285 A1; Sharma et al.; 01/2024; (“Sharma”).
Regarding Claim 1. Yin discloses A three-dimensional (3D) ferroelectric random access memory (FeRAM) (#1, Figure 3A, 3D FeRAM structure) comprising:
bit lines (#BL, Figure 3A, bit lines) extending in a first horizontal direction (Figure 3A, #BLs extend in a y-direction) on a substrate (Figure 9 shows the bit lines as being on a substrate #2) and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction (Figure 3A, #BLs are spaced apart in a z-direction perpendicular to the y-direction);
word lines disposed (#WL, Figure 3A, word lines) over the bit line (Figure 3A, the #WLs are formed over the #BLs), extending in the second horizontal direction (Figure 3A, #WLs extend in the z-direction), and spaced apart from each other in the first horizontal direction (Figure 3A, #WLs are spaced apart from each other in the y-direction);
semiconductor patterns (#114, Figure 12, channel layers which are part of #11 in Figure 3A and may be made of semiconductor material according to [0112]) arranged at intervals on corresponding portions of the word lines (Figures 3A and 12, #114s of #11s are arranged at intervals on corresponding portions of #WLs) with a gate dielectric layer therebetween (#1131, Figure 12, gate medium layer which may be a dielectric according to [0113] and formed between #114s and the gate/word lines); and
ferroelectric capacitor (FeCap) structures (#12, Figure 3A, [0071], ferroelectric capacitor) over the semiconductor patterns in [[the]] a vertical direction (Figure 3A, #12s are formed over #114s of #11s in the x-direction),
wherein the FeCap structures comprise:
a first electrode (#123, Figure 9, second capacitor electrode) comprising a body portion extending in the vertical direction from a semiconductor pattern (Figure 9, #123 is a body portion extending in the x-direction from the semiconductor channel portions of #11);
a ferroelectric layer (#122, Figure 9, capacitor layer which may be a ferroelectric according to [0129]) covering outer walls of the body portion (Figure 9, #122 covers outer walls of the body portion #123); and
second electrodes (#121, Figure 9, first capacitor electrodes) covering the ferroelectric layer (Figure 9, #121s cover outer sidewalls of #122).
Yin does not disclose that the first electrode comprises at least two horizontal extensions extending from side surfaces of the body portion in the first horizontal direction and located at different levels; and
the ferroelectric layer covers the horizontal extensions; and
the second electrodes are cover the ferroelectric layer on the horizontal extensions.
However, Sharma teaches a memory device (Figure 3) comprising word lines (#114, [0032]) and semiconductor patterns (#112, channels) with gate dielectric layers disposed between the semiconductor patterns and the word lines (#115); and
a ferroelectric capacitor structure (#120) over the semiconductor patterns, comprising:
a first electrode (#121, common plate) comprising a body portion (#323, Figure 3, central thickness of #121) extending in the vertical direction from a semiconductor pattern (Figure 3, the central thickness of #121 extends in a vertical direction away from the channels of the transistor structure) and at least two horizontal extensions extending from side surfaces of the body portion in the first horizontal direction and located at different levels (#321, Figure 3, greater thickness regions of #121 which are horizontal extensions from the side of the body portion located at different vertical levels);
a ferroelectric layer (#125, [0027], ferroelectric insulator layer) covering outer walls of the body portion and the horizontal extensions (Figure 3, #125 covers outer walls of the central body and lateral extensions of #121); and
second electrodes (#130, Figure 3, plate lines) covering the ferroelectric layer on the horizontal extensions (Figure 3, #130 covers #125 on the lateral extensions of #121).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the horizontal extensions of the first electrode to extend into the ferroelectric layer and second electrode in the device of Yin as was done by Sharma since this structure provides a greater capacitance with similar capacitor volume and external dimensions (see [0045] of Sharma)
Regarding Claim 2. Yin in view of Sharma disclose The 3D FeRAM of claim 1, wherein, between the horizontal extensions, the body portion has a quadrangular shape (Yin, Figure 9, the entirety of the body portion #123 has a quadrangular shape in the side view; Sharma, Figure 3, the central portion of #121 between the lateral extensions has a quadrangular shape in the side view), and the ferroelectric layer covering the outer walls of the body portion has a quadrangular ring-like shape (Yin, Figures 3 and 9, #122 has a quadrangular, elongated vertical rectangle, ring-like shape in the side view; Sharma, Figure 3, the portion of #125 covering the outer sidewalls of the body portion of #121 has a quadrangular ring-like shape in the side view provided).
Regarding Claim 3. Yin in view of Sharma disclose The 3D FeRAM of claim 1, wherein a horizontal extension has a shape of a quadrangular pillar oriented in the first horizontal direction (Sharma, Figure 3, the laterally extending portions of #121 have the shape of a quadrangular pillar oriented along the left-right horizontal direction in the side view provided).
Regarding Claim 4. Yin in view of Sharma disclose The 3D FeRAM of claim 3, wherein the ferroelectric layer of the horizontal extension has a shape of a quadrangular tube oriented in the first horizontal direction with a distal end closed (Sharma, Figure 3, the portions of #125 on the laterally extending portions of #121 have the shape of a quadrangular tube oriented along the left-right horizontal direction in the side view provided with a distal end closed),
a cross-section of the ferroelectric layer of the horizontal extension perpendicular to the first horizontal direction has a quadrangular ring-like shape (Sharma, Figure 3, based on Figure 2 showing a complete wrap around of the ferroelectric layer around the central electrode, a cross section of #125 in-out of the page would also have a quadrangular ring-like shape), and
a cross-section of the ferroelectric layer of the horizontal extension perpendicular to the second horizontal direction has a ‘⊏’ shape (Sharma, Figure 3, the portions of #125 on the laterally extending portions of #121 in the left-right horizontal direction which is perpendicular to the in-out of the page direction has a ‘⊏’ shape at the ends).
Regarding Claim 5. Yin in view of Sharma disclose The 3D FeRAM of claim 3, wherein the second electrode has a shape of a quadrangular tube oriented in the first horizontal direction with a distal end closed (Sharma, Figure 3, the portions of #130 on the laterally extending portions of #121 have the shape of a quadrangular tube oriented along the left-right horizontal direction in the side view provided with a distal end closed),
a cross-section of the second electrode perpendicular to the first horizontal direction has a quadrangular ring-like shape (Sharma, Figure 3, based on Figure 2 showing a complete wrap around of #130 around the central electrode, a cross section of #130 in-out of the page would also have a quadrangular ring-like shape), and
a cross-section of the second electrode perpendicular to the second horizontal direction has a ‘⊏’ shape (Sharma, Figure 3, the portions of #130 on the laterally extending portions of #121 in the left-right horizontal direction which is perpendicular to the in-out of the page direction has a ‘⊏’ shape).
Regarding Claim 6. Yin in view of Sharma disclose The 3D FeRAM of claim 5, wherein the closed distal end of the quadrangular tube-like portion of the second electrode is thicker than four sides of the quadrangular tube-like portion of the second electrode (Sharma, Figure 3, the portions of #130 at the closed end of the shape are thicker than the portions which wrap around the upper, lower, and side surfaces of #125 due to the inclusion of the thick #132 portion), and
the second electrode comprises an extension (Yin, Figure 3A, the plates include and extension portion which extends in both horizontal directions; Sharma, #134, Figure 3, vertical portion) extending from the closed distal end of the quadrangular tube-like portion in the second horizontal direction (Yin Figure 3A and Sharma Figure 3, both extension portions are three-dimensional such that they necessarily extend in from the portion that wraps around the central electrode and in both horizontal directions), and
second electrodes located at a same level in the vertical direction are connected to each other through the extension (Yin, Figure 3A, the plates form one continuous second electrode structure at each vertical level; Sharma, Figure 3, all of the parts of the device are necessarily physically connected either directly or indirectly).
Regarding Claim 7. Yin in view of Sharma disclose The 3D FeRAM of claim 1, wherein an etch stop layer (Yin, #1501, Figure 9, insulating portion which may be made of a different material than materials it is adjacent to, see [0091], such that it necessarily has different etching properties and may function as an etch stop layer) is on a surface of the substrate over the bit lines, word lines, and semiconductor patterns (Yin, Figure 9, #1501 is on a top surface of #2 over the bit lines (#14), the word lines (#WLs of #11), and the channel semiconductor portions (#114s of #11)), and
the body portion penetrates the etch stop layer and is electrically connected to the semiconductor patterns (Yin, Figure 9, the body portion of #123 penetrates #1501 and is electrically connected to the channel of the transistors #11).
Regarding Claim 8. Yin in view of Sharma disclose The 3D FeRAM of claim 1, wherein the word lines are arranged on both sides of the semiconductor pattern in the first direction (Yin, Figures 3A and 9, the word lines are arranged to wrap around both sides of the central channel portions in the y-direction), and
the semiconductor pattern comprises a channel region in a central portion of the semiconductor pattern in the vertical direction (Yin, Figure 12, #114 of #11 is a channel portion in the central region in a vertical direction of the transistor; Sharma, Figure 12, the middle #112 of #110 is a channel portion in the central region of the transistor in a vertical direction) and impurity regions between the channel region and the bit lines, and between the channel region and the body portion in the vertical direction (Yin, Figures 9 and 12, [0104], the transistor includes a source and drain, i.e. doped regions, connected to the respective upper and lower electrodes between the channel region and the body portion and bit lines respectively).
Regarding Claim 12. Yin discloses A three-dimensional (3D) ferroelectric random access memory (FeRAM) (#1, Figure 3A, 3D FeRAM structure) comprising:
a substrate (#2, Figure 9, substrate);
bit lines (#BL, Figure 3A, bit lines) extending in a first horizontal direction (Figure 3A, #BLs extend in a y-direction) on the substrate (Figure 9 shows the bit lines as being on substrate #2) and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction (Figure 3A, #BLs are spaced apart in a z-direction perpendicular to the y-direction);
a selection transistor (Tr) (#11, Figure 3, transistor) comprising word lines (#WLs, Figure 3A, word lines and #1132, Figure 12, [0077], metal gate of the transistor which the word lines are connected to) arranged over the bit lines in a vertical direction (Figure 3A, the #WLs and #1132s are formed over the #BLs in the x-direction), extending in the second horizontal direction (Figure 3A, #WLs and #1132s extend in the z-direction), and spaced apart from each other in the first horizontal direction (Figure 3A, #WLs and #1132s are spaced apart from each other in the y-direction), and semiconductor patterns (#114, Figure 12, channel layers which are part of #11 in Figure 3A and may be made of semiconductor material according to [0112]) arranged at intervals on corresponding portions of the word lines (Figures 3A and 12, #114s of #11s are arranged at intervals on corresponding portions of #WLs and #1132s) with a gate dielectric layer therebetween in the second horizontal direction (#1131, Figures 3A and 12, gate medium layer which may be a dielectric according to [0113] and formed between #114s and the gate/word lines in both the y-direction and the z-direction); and
a FeCap structure (plurality of #12, Figure 3A, [0071], ferroelectric capacitors) having a plurality of capacitors on the selection Tr (Figure 3A, each #12 which is over a respective #11)
wherein the FeCap structure comprises:
a first electrode (#123, Figure 9, second capacitor electrode) comprising a body portion extending in the vertical direction from a semiconductor pattern (Figure 9, #123 is a body portion extending in the x-direction from the semiconductor channel portions of #11);
a ferroelectric layer (#122, Figure 9, capacitor layer which may be a ferroelectric according to [0129]) covering outer walls of the body portion (Figure 9, #122 covers outer walls of the body portion #123); and
a plurality of second electrodes (#121, Figure 9, first capacitor electrodes) covering the ferroelectric layer (Figure 9, #121s cover outer sidewalls of #122),
wherein the 3D FeRAM has a structure in which the plurality of FeCaps are electrically connected to one selection Tr (Figure 3A, a plurality of #12s, at least four are observed, are electrically connected to each #11).
Yin does not disclose that the first electrode comprises[[ n]] horizontal extensions extending from a side surface of the body portion in the first horizontal direction; and
the ferroelectric layer covers the horizontal extensions; and
the second electrodes covering the ferroelectric layer of the horizontal extensions.
However, Sharma teaches a memory device (Figure 3) comprising word lines (#114, [0032]) and semiconductor patterns (#112, channels) with gate dielectric layers disposed between the semiconductor patterns and the word lines (#115); and
a ferroelectric capacitor structure (#120) over the semiconductor patterns, comprising:
a first electrode (#121, common plate) comprising a body portion (#323, Figure 3, central thickness of #121) extending in the vertical direction from a semiconductor pattern (Figure 3, the central thickness of #121 extends in a vertical direction away from the channels of the transistor structure) and at least two horizontal extensions extending from side surfaces of the body portion in the first horizontal direction and located at different levels (#321, Figure 3, greater thickness regions of #121 which are horizontal extensions from the side of the body portion located at different vertical levels);
a ferroelectric layer (#125, [0027], ferroelectric insulator layer) covering outer walls of the body portion and the horizontal extensions (Figure 3, #125 covers outer walls of the central body and lateral extensions of #121); and
second electrodes (#130, Figure 3, plate lines) covering the ferroelectric layer on the horizontal extensions (Figure 3, #130 covers #125 on the lateral extensions of #121).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the horizontal extensions of the first electrode to extend into the ferroelectric layer and second electrode in the device of Yin as was done by Sharma since this structure provides a greater capacitance with similar capacitor volume and external dimensions (see [0045] of Sharma)
Regarding Claim 13. Yin in view of Sharma disclose The 3D FeRAM of claim 12, wherein the horizontal extensions have a shape of a quadrangular pillar oriented in the first horizontal direction (Sharma, Figure 3, the laterally extending portions of #121 have the shape of a quadrangular pillar oriented along the left-right horizontal direction in the side view provided),
the ferroelectric layer of the horizontal extension has a shape of a quadrangular tube with a distal end closed in the first horizontal direction (Sharma, Figure 3, the portions of #125 on the laterally extending portions of #121 have the shape of a quadrangular tube oriented along the left-right horizontal direction in the side view provided with a distal end closed),
a cross-section of the ferroelectric layer of the horizontal extension perpendicular to the first horizontal direction has a quadrangular ring-like shape (Sharma, Figure 3, based on Figure 2 showing a complete wrap around of the ferroelectric layer around the central electrode, a cross section of #125 in-out of the page would also have a quadrangular ring-like shape), and
a cross-section of the ferroelectric layer of the horizontal extension perpendicular to the second horizontal direction has a ‘⊏’ shape (Sharma, Figure 3, the portions of #125 on the laterally extending portions of #121 in the left-right horizontal direction which is perpendicular to the in-out of the page direction has a ‘⊏’ shape at the ends).
Regarding Claim 14. Yin in view of Sharma disclose The 3D FeRAM of claim 12, wherein the second electrode has a shape of a quadrangular tube with a distal end closed in the first horizontal direction (Sharma, Figure 3, the portions of #130 on the laterally extending portions of #121 have the shape of a quadrangular tube oriented along the left-right horizontal direction in the side view provided with a distal end closed),
a cross-section of the second electrode perpendicular to the first horizontal direction has a quadrangular ring-like shape (Sharma, Figure 3, based on Figure 2 showing a complete wrap around of #130 around the central electrode, a cross section of #130 in-out of the page would also have a quadrangular ring-like shape),
a cross-section of the second electrode perpendicular to the second horizontal direction has a ‘⊏’ shape (Sharma, Figure 3, the portions of #130 on the laterally extending portions of #121 in the left-right horizontal direction which is perpendicular to the in-out of the page direction has a ‘⊏’ shape),
the second electrode comprises an extension (Yin, Figure 3A, the plates include and extension portion which extends in both horizontal directions; Sharma, #134, Figure 3, vertical portion) extending from a closed side of a quadrangular tube-like portion in the second horizontal direction (Yin Figure 3A and Sharma Figure 3, both extension portions are three-dimensional such that they necessarily extend in from the portion that wraps around the central electrode and in both horizontal directions), and
second electrodes located at a same level in the vertical direction are connected to each other through the extension (Yin, Figure 3A, the plates form one continuous second electrode structure at each vertical level; Sharma, Figure 3, all of the parts of the device are necessarily physically connected either directly or indirectly).
Regarding Claim 15. Yin in view of Sharma disclose The 3D FeRAM of claim 12, wherein an etch stop layer (Yin, #1501, Figure 9, insulating portion which may be made of a different material than materials it is adjacent to, see [0091], such that it necessarily has different etching properties and may function as an etch stop layer) is on an entire surface of the substrate over the bit lines, word lines, and semiconductor patterns (Yin, Figure 9, #1501 is on an entire top surface of #2 over the bit lines (#14), the word lines (#WLs of #11), and the channel semiconductor portions (#114s of #11)),
the word lines are arranged on both sides of the semiconductor pattern in the first direction (Yin, Figures 3A and 9, the word lines are arranged to wrap around both sides of the central channel portions in the y-direction),
the semiconductor pattern comprises a channel region in a central portion of the semiconductor pattern in the vertical direction (Yin, Figure 12, #114 of #11 is a channel portion in the central region in a vertical direction of the transistor; Sharma, Figure 12, the middle #112 of #110 is a channel portion in the central region of the transistor in a vertical direction) and impurity regions between the channel region and the bit lines and between the channel region and the body portion in the vertical direction (Yin, Figures 9 and 12, [0104], the transistor includes a source and drain, i.e. doped regions, connected to the respective upper and lower electrodes between the channel region and the body portion and bit lines respectively), and
the body portion penetrates the etch stop layer and is connected to the impurity regions (Yin, Figure 9, the body portion of #123 penetrates #1501 and is electrically connected to the channel of the transistors #11).
Regarding Claim 16. Yin discloses A three-dimensional (3D) ferroelectric random access memory (FeRAM) (#1, Figure 3A, 3D FeRAM structure) comprising:
a substrate (#2, Figure 9, substrate);
bit lines (#BL, Figure 3A, bit lines) extending in a first horizontal direction (Figure 3A, #BLs extend in a y-direction) on the substrate (Figure 9 shows the bit lines as being on substrate #2) and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction (Figure 3A, #BLs are spaced apart in a z-direction perpendicular to the y-direction);
at least one transistor (TR) (#11, Figure 3, transistor) on the bit line (Figure 3, the encircled #11 is located on one of the #BLs; and
a FeCap structure (plurality of #12, Figure 3A, [0071], ferroelectric capacitors) on the at least one TR (Figure 3A, each #12 which is over a respective #11),
wherein the FeCap structure comprises:
a first electrode (#123, Figure 9, second capacitor electrode) comprising a body portion extending in a vertical direction from the at least one Tr (Figure 9, #123 is a body portion extending in the x-direction from #11);
a ferroelectric layer (#122, Figure 9, capacitor layer which may be a ferroelectric according to [0129]) covering outer walls of the body portion (Figure 9, #122 covers outer walls of the body portion #123); and
a plurality of second electrodes (#121, Figure 9, first capacitor electrodes) covering the ferroelectric layer (Figure 9, #121s cover outer sidewalls of #122).
Yin does not disclose that the first electrode comprises a plurality of horizontal extensions extending in the first horizontal direction from a side surface of the body portion and located at different levels; and
the ferroelectric layer covers the horizontal extensions; and
the second electrodes covering the ferroelectric layer on the horizontal extensions.
However, Sharma teaches a memory device (Figure 3) comprising word lines (#114, [0032]) and semiconductor patterns (#112, channels) with gate dielectric layers disposed between the semiconductor patterns and the word lines (#115); and
a ferroelectric capacitor structure (#120) over the semiconductor patterns, comprising:
a first electrode (#121, common plate) comprising a body portion (#323, Figure 3, central thickness of #121) extending in the vertical direction from a semiconductor pattern (Figure 3, the central thickness of #121 extends in a vertical direction away from the channels of the transistor structure) and at least two horizontal extensions extending from side surfaces of the body portion in the first horizontal direction and located at different levels (#321, Figure 3, greater thickness regions of #121 which are horizontal extensions from the side of the body portion located at different vertical levels);
a ferroelectric layer (#125, [0027], ferroelectric insulator layer) covering outer walls of the body portion and the horizontal extensions (Figure 3, #125 covers outer walls of the central body and lateral extensions of #121); and
second electrodes (#130, Figure 3, plate lines) covering the ferroelectric layer on the horizontal extensions (Figure 3, #130 covers #125 on the lateral extensions of #121).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the horizontal extensions of the first electrode to extend into the ferroelectric layer and second electrode in the device of Yin as was done by Sharma since this structure provides a greater capacitance with similar capacitor volume and external dimensions (see [0045] of Sharma)
Regarding Claim 17. Yin in view of Sharma disclose The 3D FeRAM of claim 16, wherein the at least one TR comprises one selection Tr (Yin, Figure 3A, let the circled #11 be a selection transistor), and
the one selection Tr comprises:
word lines (Yin, #WLs, Figure 3A, word lines and #1132, Figure 12, [0077], metal gate of the transistor which the word lines are connected to) disposed over the bit line in a vertical direction (Yin, Figure 3A, the #WLs and #1132s are formed over the #BLs in the x-direction), extending in the second horizontal direction (Yin, Figure 3A, #WLs and #1132s extend in the z-direction), and spaced apart from each other in the first horizontal direction (Yin, Figure 3A, #WLs and #1132s are spaced apart from each other in the y-direction);
channel regions (Yin, Figure 12, #114 of #11 is a channel portion in the central region in a vertical direction of the transistor; Sharma, Figure 12, the middle #112 of #110 is a channel portion in the central region of the transistor in a vertical direction) arranged at intervals on corresponding portions of the word lines (Yin, Figures 3A and 12, #114s of #11s are arranged at intervals on corresponding portions of #WLs and #1132s) with a gate dielectric layer therebetween in the second horizontal direction (Yin, #1131, Figures 3A and 12, gate medium layer which may be a dielectric according to [0113] and formed between #114s and the gate/word lines in both the y-direction and the z-direction); and
impurity regions arranged on both sides of the channel regions in the vertical direction (Yin, Figures 9 and 12, [0104], the transistor includes a source and drain, i.e. doped regions, connected to the respective upper and lower electrodes between the channel region and the body portion and bit lines respectively).
Regarding Claim 18. Yin in view of Sharma disclose The 3D FeRAM of claim 17, wherein a horizontal extension has a shape of a quadrangular pillar laid down in the first horizontal direction (Sharma, Figure 3, the laterally extending portions of #121 have the shape of a quadrangular pillar oriented along the left-right horizontal direction in the side view provided), and,
when the first electrode, the ferroelectric layer of the horizontal extensions, and the second electrode constitute one FeCap (Yin, Figure 9, each #12 comprises a #121, a #122, and a #123; Sharma, Figure 3, each #120 comprises a #121, #125, and #130), the 3D FeRAM has a structure in which a plurality of FeCaps are connected to the one selection Tr (Yin, Figure 3A, a plurality of #12s, at least four are observed, are electrically connected to each #11).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER JAMES WIEGAND whose telephone number is (571)270-0096. The examiner can normally be reached Mon-Fri. 8AM-5PM.
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/TYLER J WIEGAND/Examiner, Art Unit 2812
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