Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Specification Objection
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections – 35 U.S.C. 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AlA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-8, 10 and 16 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (U.S. Patent Pub. No. 2023/0126337).
Regarding Claim 1
FIG. 1 of Kim discloses a power semiconductor device, comprising: a high voltage circuit (30) configured to output high voltage; a low voltage circuit (35) configured to output low voltage; a capacitor (20) configured to be electrically connected to the high voltage circuit, the capacitor being configured to provide power to the high voltage circuit while the high voltage is output; a switching circuit (10) configured to be electrically connected to the high voltage circuit and the capacitor, the switching circuit being configured to connect the capacitor to a driving power supply (VCC) to charge the capacitor while the low voltage is output, the switching circuit being configured to prevent the high voltage circuit and the driving power supply from being electrically connected to each other while the high voltage is output; and a resistor (15) configured to be electrically connected between the switching circuit and the high voltage circuit, the resistor being configured to drop the high voltage to a voltage lower than a breakdown voltage of the switching circuit while the high voltage is output, wherein the resistor (FIG. 3) comprises: a deep well region (112) of a second conductivity type (n) [0043] disposed within a substrate (101); a field oxide film (150) disposed on a surface of the substrate [0050]; and a P-TOP region (180) spaced apart from the field oxide film and disposed within the deep well region [0049].
Regarding Claim 2
FIG. 3of Kim discloses the P-TOP region (180) is disposed below the field oxide film (150) and spaced apart from a bottom of the field oxide film.
Regarding Claim 3
FIG. 3 of Kim discloses the P-TOP region (180) is disposed within the deep well region (112) and spaced apart from a bottom surface of the deep well region.
Regarding Claim 4
FIG. 3 of Kim discloses the switching circuit a bipolar junction transistor [0048].
Regarding Claim 5
FIG. 7 of Kim discloses the resistor further comprises: a first electrode layer (181) configured to be electrically connected to a ground terminal (185) on the field oxide film on an area adjacent to the switching circuit; and a second electrode layer (280) configured to be electrically connected to the high voltage circuit on the field oxide film on an area adjacent to the high voltage circuit.
Regarding Claim 6
FIG. 7 of Kim discloses the resistor further comprises: a first contact region (120) disposed in the deep well region (112), the first contact region being configured to be electrically connected to the switching circuit [0049]; and a second contact region (140) spaced apart from the first contact region within the deep well region, the second contact region being configured to be electrically connected to the high voltage circuit [0051].
Regarding Claim 7
FIG. 3 of Kim discloses the resistor further comprises: a buried layer (105) of a second conductivity type disposed below the second contact region [0043].
Regarding Claim 8
FIG. 3 of Kim discloses the resistor further comprises: a single electrode layer (250) disposed on the field oxide film (150).
Regarding Claim 10
FIG. 3 of Kim discloses the switching circuit comprises: a diode (D3) disposed on the substrate.
Regarding Claim 16
FIG. 1 of Kim discloses a power semiconductor device, comprising: a high voltage circuit (30) configured to output high voltage; a low voltage circuit (35) configured to output low voltage; a capacitor (20) configured to be electrically connected to the high voltage circuit, the capacitor being configured to provide power to the high voltage circuit while the high voltage is output; a switching circuit (10) configured to be electrically connected to the high voltage circuit and the capacitor, the switching circuit being configured to connect the capacitor to a driving power supply (VCC) to charge the capacitor while the low voltage is output, the switching circuit being configured to prevent the high voltage circuit and the driving power supply from being electrically connected to each other while the high voltage is output; and a resistor (15) configured to be electrically connected between the switching circuit and the high voltage circuit, the resistor being configured to drop the high voltage to a voltage lower than a breakdown voltage of the switching circuit while the high voltage is output, wherein the resistor (FIG. 3) comprises: a deep well region (112) of a second conductivity type (n) [0042] disposed within a substrate (101); a field oxide film (150) disposed on a surface of the substrate [0050]; and a P-TOP region (180) spaced apart from the field oxide film and disposed within the deep well region [0049].
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-8, 10, 11 and 16 rejected under 35 U.S.C. 103 as being unpatentable over Hano (U.S. Patent Pub. No. 2003/0218186), in view of Chan (U.S. Patent Pub. No. 2014/0191792)
Regarding Claim 1
FIG. 1 of Hano discloses a power semiconductor device, comprising: a high voltage circuit (111) configured to output high voltage; a low voltage circuit (112) configured to output low voltage; a capacitor (C1) configured to be electrically connected to the high voltage circuit, the capacitor being configured to provide power to the high voltage circuit while the high voltage is output; a switching circuit (D3) configured to be electrically connected to the high voltage circuit and the capacitor, the switching circuit being configured to connect the capacitor to a driving power supply (VCC) to charge the capacitor while the low voltage is output, the switching circuit being configured to prevent the high voltage circuit and the driving power supply from being electrically connected to each other while the high voltage is output; and a resistor (Rn) configured to be electrically connected between the switching circuit and the high voltage circuit [0057], the resistor being configured to drop the high voltage to a voltage lower than a breakdown voltage of the switching circuit while the high voltage is output, wherein the resistor (FIG. 2) comprises: a deep well region (106) of a second conductivity type (n) disposed within a substrate (105); and a P-TOP region (19, FIG. 7) disposed within the deep well region.
Hano is silent with respect to “a field oxide film disposed on a surface of the substrate; and a P-TOP region spaced apart from the field oxide film and disposed within the deep well region”.
FIG. 2 of Chan discloses a similar power semiconductor device, comprising a field oxide film (18) disposed on a surface of the substrate; and a P-TOP region (19) [0024] spaced apart from the field oxide film and disposed within the deep well region (12).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Hano, as taught by Chan. The ordinary artisan would have been motivated to modify Hano in the above manner for purpose of scaling the output current based on demand ([0005] of Chan).
Regarding Claim 2
FIG. 2 of Chan discloses the P-TOP region (19) is disposed below the field oxide film (18) and spaced apart from a bottom of the field oxide film.
Regarding Claim 3
FIG. 2 of Chan discloses the P-TOP region (19) is disposed within the deep well region (12) and spaced apart from a bottom surface of the deep well region.
the resistor further comprises: a first contact region disposed in the deep well region, the first contact region being configured to be electrically connected to the switching circuit; and a second contact region spaced apart from the first contact region within the deep well region, the second contact region being configured to be electrically connected to the high voltage circuit.
Regarding Claim 4
FIG. 27 of Hano discloses the switching circuit (101) comprises a bipolar junction transistor (109).
Regarding Claim 5
FIG. 2 of Hano discloses the resistor further comprises: a first electrode layer configured to be electrically connected to a ground terminal on the field oxide film on an area adjacent to the switching circuit; and a second electrode layer configured to be electrically connected to the high voltage circuit on the field oxide film on an area adjacent to the high voltage circuit.
Regarding Claim 6
FIG. 2 of Hano discloses the resistor further comprises: a first contact region (12) disposed in the deep well region (106), the first contact region being configured to be electrically connected to the switching circuit (6); and a second contact region (11) spaced apart from the first contact region within the deep well region, the second contact region being configured to be electrically connected to the high voltage circuit.
Regarding Claim 7
FIG. 2 of Hano discloses the resistor further comprises: a buried layer (n+) of a second conductivity type disposed below the second contact region.
Regarding Claim 8
FIG. 2 of Hano discloses the resistor further comprises: a single electrode layer disposed on the field oxide film.
Regarding Claim 10
FIG. 2 of Hano discloses the switching circuit comprises: a diode (D3) disposed on the substrate.
Regarding Claim 11
FIG. 2 of Hano discloses the switching circuit comprises: a field oxide film disposed on the surface of the substrate; and a positive electrode layer (connected to 14) and a negative electrode layer (connected to 11) disposed on the field oxide film on the surface of the substrate
Regarding Claim 16
FIG. 1 of Hano discloses a power semiconductor device, comprising: a high voltage circuit (111) configured to output high voltage; a low voltage circuit (112) configured to output low voltage; a capacitor (C1) configured to be electrically connected to the high voltage circuit, the capacitor being configured to provide power to the high voltage circuit while the high voltage is output; a switching circuit (D3) configured to be electrically connected to the high voltage circuit and the capacitor, the switching circuit being configured to connect the capacitor to a driving power supply (VCC) to charge the capacitor while the low voltage is output, the switching circuit being configured to prevent the high voltage circuit and the driving power supply from being electrically connected to each other while the high voltage is output; and a resistor (Rn) configured to be electrically connected between the switching circuit and the high voltage circuit, the resistor being configured to drop the high voltage to a voltage lower than a breakdown voltage of the switching circuit while the high voltage is output, wherein the resistor (FIG. 2) comprises: a deep well region (106) of a second conductivity type (n) disposed within a substrate (105); and a P-TOP region (19, FIG. 7) disposed within the deep well region.
Hano is silent with respect to “a field oxide film disposed on a surface of the substrate; and a P-TOP region spaced apart from the field oxide film and disposed within the deep well region”.
FIG. 2 of Chan discloses a similar power semiconductor device, comprising a field oxide film (18) disposed on a surface of the substrate; and a P-TOP region (19) [0024] spaced apart from the field oxide film and disposed within the deep well region (12).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Hano, as taught by Chan. The ordinary artisan would have been motivated to modify Hano in the above manner for purpose of scaling the output current based on demand ([0005] of Chan).
Claim 9 rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of Choi (U.S. Patent Pub. No. 2010/0271079).
Regarding Claim 9
Kim discloses Claim 8, wherein the single electrode layer (250) includes a polysilicon film.
Kim is silent with respect to “doped with impurities of a second conductivity type”.
FIG. 9 of Choi discloses a similar power semiconductor device, comprising single electrode layer (165) disposed on the field oxide film, wherein the single electrode layer includes a polysilicon film [0012] doped with impurities of a second conductivity type (n) [0101].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Kim, as taught by Choi. The ordinary artisan would have been motivated to modify Kim in the above manner for purpose of improving conductivity.
Claims 9, 11 and 12 rejected under 35 U.S.C. 103 as being unpatentable over Hano and Chan, in view of Choi.
Regarding Claim 9
Hano as modified by Chan discloses Claim 8, wherein the single electrode layer is doped with impurities of a second conductivity type.
Hano as modified by Chan is silent with respect to “the single electrode layer includes a polysilicon film doped with impurities of a second conductivity type”.
FIG. 9 of Choi discloses a similar power semiconductor device, comprising single electrode layer (165) disposed on the field oxide film, wherein the single electrode layer includes a polysilicon film [0012] doped with impurities of a second conductivity type (n) [0101].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Kim, as taught by Choi. The ordinary artisan would have been motivated to modify Kim in the above manner for purpose of improving conductivity.
Regarding Claim 11
FIG. 9 of Choi discloses the switching circuit comprises: a field oxide film (140) disposed on the surface of the substrate; and a positive electrode layer (150) and a negative electrode layer (151) disposed on the field oxide film on the surface of the substrate
Regarding Claim 12
FIG. 9 of Choi discloses the positive electrode layer (150) includes a polysilicon film doped with impurities of a first conductivity type [0094].
Claim 13 rejected under 35 U.S.C. 103 as being unpatentable over Hano and Chan, in view of Renaud (U.S. Patent Pub. No. 2010/0127305).
Regarding Claim 13
Hano as modified by Chan discloses Claim 4.
Hano as modified by Chan is silent with respect to “the bipolar junction transistor comprises: an emitter region of a second conductivity type disposed on the surface of the substrate; a base region of a first conductivity type spaced apart from the emitter region, the base region being disposed on the surface of the substrate; and a collector region spaced apart from the emitter region and the base region, the collector region being disposed on the surface of the substrate”.
FIG. 3 of Renaud discloses a similar power semiconductor device, wherein the bipolar junction transistor comprises: an emitter region (24) of a second conductivity type (n) disposed on the surface of the substrate (14); a base region (22) of a first conductivity type (p) spaced apart from the emitter region, the base region being disposed on the surface of the substrate; and a collector region (20) spaced apart from the emitter region and the base region, the collector region being disposed on the surface of the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Kim, as taught by Renaud. The ordinary artisan would have been motivated to modify Kim in the above manner for purpose of providing ESD protection ([0012] of Renaud).
Claims 14 and 15 rejected under 35 U.S.C. 103 as being unpatentable over Hano, Renaud, in view of Liaw (U.S. Patent Pub. No. 2007/0181948).
Regarding Claim 14
Hano as modified by Chan and Renaud discloses Claim 13.
Hano as modified by Renaud is silent with respect to “the base region and the collector region are configured to be electrically connected to the driving power supply”.
FIG. 13 of Liaw discloses a similar power semiconductor device, wherein the base region and the collector region are configured to be electrically connected to the driving power supply.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Kim, as taught by Liaw. The ordinary artisan would have been motivated to modify Kim in the above manner for purpose of providing ESD protection ([0012] of Liaw).
Regarding Claim 15
FIG. 13 of Liaw discloses the emitter region is configured to be electrically connected to the resistor.
Pertinent Art
Pertinent art includes Uno (JP 2006005182), CN 113764281, KR 20230057074, and US 20080087912, 20170148873, 20220037525, 20190013403.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897