DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I, Species A, claims 1-7, 9-15, and 17-18 in the reply filed on 5/22/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Rejection 1/2
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 5-7, and 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tanaka et al. (US 2022/0285504).
(Re Claim 1) Tanaka teaches a nitride semiconductor device, comprising: a gallium nitride layer (121+122; Fig. 20B) having a first principal face (10a; Fig. 20B) and a second principal face (10b; Fig. 20B), the second principal face being located on opposite side of the first principal face (Fig. 20B); and a field effect transistor (121+30+20+18+21+23+25; Fig. 20B) formed in the gallium nitride layer, the field effect transistor including:
a gate insulator film (21; Fig. 20B) formed on the gallium nitride layer on a side (topside; Fig. 20B) of the first principal face;
a p type region (20+14; Fig. 20B) formed in the gallium nitride layer, the p type region being in contact with the gate insulator film;
an n type region (center 18 on the left; Fig. 20B) formed in the gallium nitride layer, the n type region being in contact with the p type region in a first direction (left to right; Fig. 20B) parallel to an interface (coextensive with contact between left region 14 and gate insulator film 21; Fig. 20B) between the p type region and the gate insulator film; and a first electrode (25 on the left; Fig. 20B) disposed on the side of the first principal face, the first electrode being in contact with the n type region (Fig. 20B), wherein the p type region includes:
a first region (left region 14; Fig. 20B) being in contact with the gate insulator film; and a second region (the region 20 that is to the right of the leftmost 20; Fig. 20B) being in contact with the gate insulator film (Fig. 20B) and lying in the first direction between the first region and the n type region (between the center 18 on the left and the left 14; Fig. 20B), wherein the second region has a higher concentration of p type impurities than the first region (¶154), wherein the field effect transistor further including:
a p type high-concentration region (left 30; Fig. 20B) formed in the gallium nitride layer, the high-concentration region being located between the n type region and the second principal face (Fig. 20B), wherein the high-concentration region has a higher concentration of p type impurities than the first region (¶94) and is in contact with the second region, wherein the high-concentration region has a higher concentration of p type impurities than the second region (¶¶94, 154).
(Re Claim 3) Tanaka teaches the nitride semiconductor device according to claim 1, wherein the first region and the second region exist in a channel region (a channel region extends between source regions and across gate insulation; Fig. 20B markup) of the field effect transistor.
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(Re Claim 5) Tanaka teaches the nitride semiconductor device according to claim 1, wherein a peak position (in the center of the Mg concentration sustaining region, as depicted in Fig. 13, that is closest to the region 18 that is closest to the gate insulating film as seen in Fig. 20B; ¶185) exists in the p type region, the peak position being a position where a concentration of p type impurities is the highest in the first direction (maximum concentration is within the Mg concentration sustaining region; Fig. 13, ¶185), wherein the peak position exists in the second region (within the rightmost region 202; ¶185).
(Re Claim 6) Tanaka teaches the nitride semiconductor device according to claim 1, wherein the second region is in contact with the n type region (Fig. 20B).
(Re Claim 7) Tanaka teaches the nitride semiconductor device according to claim 1, wherein the high-concentration region is in contact with the n type region (Fig. 20B).
(Re Claim 9) Tanaka teaches the nitride semiconductor device according to claim 1, wherein the high-concentration region is in contact with the first region (Fig. 20B).
(Re Claim 10) Tanaka teaches the nitride semiconductor device according to claim 1, the field effect transistor further including:
a second electrode (27; Fig. 20B) formed on the side of the second principal face (Fig. 20B).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over (US 2022/0285504) as applied to claim 1 above.
(Re Claim 4) Tanaka teaches the nitride semiconductor device according to claim 1, but has not been explicitly shown to teach an on-state current of the field effect transistor flows from a side of the second principal face of the gallium nitride layer through the first region and the second region to the n type region.
However, as the prior art has been shown to be identical to the claimed structure of the invention, a person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious that Tanaka’s claimed device would also direct on-state current to flow through the claimed path. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). "When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not." See MPEP 2112, particularly 2112.01.
Claims 2, 11-15, and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka et al. (US 2022/0285504).
(Re Claim 2) Tanaka teaches the nitride semiconductor device, comprising: a gallium nitride layer (121+122; Fig. 20B) having a first principal face (10a; Fig. 20B) and a second principal face (10b; Fig. 20B), the second principal face being located on opposite side of the first principal face (Fig. 20B); and a field effect transistor (121+30+20+18+21+23+25; Fig. 20B) formed in the gallium nitride layer, the field effect transistor including:
a gate insulator film (21; Fig. 20B) formed on the gallium nitride layer on a side (topside; Fig 20B) of the first principal face;
a p type region (20+14; Fig. 20B) formed in the gallium nitride layer, the p type region being in contact with the gate insulator film (Fig. 20B);
an n type region (center 18 on the left; Fig. 20B) formed in the gallium nitride layer, the n type region being in contact with the p type region in a first direction (left to right) parallel to an interface (coextensive with contact between left region 14 and gate insulator film 21; Fig. 20B) between the p type region and the gate insulator film; and a first electrode (25 on the left; Fig. 20B) disposed on the side of the first principal face, the first electrode being in contact with the n type region (Fig. 20B), wherein the p type region includes:
a first region (left region 14; Fig. 20B) being in contact with the gate insulator film; and a second region (the region 20 that is to the right of the leftmost 20; Fig. 20B) being in contact with the gate insulator film and lying in the first direction between the first region and the n type region (between the center 18 on the left and the left 14; Fig. 20B), wherein the second region has a higher concentration of p type impurities than the first region (¶154), wherein the field effect transistor further including:
a p type high-concentration region (left 30; Fig. 20B) formed in the gallium nitride layer, the high-concentration region being located between the n type region and the second principal face (Fig. 20B), wherein the high-concentration region has a higher concentration of p type impurities than the first region (¶94) and is in contact with the second region, wherein the concentration of p type impurities in the high-concentration region is 5x1018cm-3 or more but less than 1x1020 cm-3 (¶180), and wherein the concentration of p type impurities in the first region is 1x1016 cm-3 or more but less than 1 x1018 cm-3 (¶94).
Tanaka has not been explicitly shown to teach the concentration of p type impurities in the second region is 1x1018 cm-3 or more but less than 5x1018 cm-3.
However, Tanaka does teach that the concentration of p-type impurities in the second region is 1x1019 cm-3 (¶188).
The values for the concentration of p-type impurities taught by Tanaka are sufficiently close to those claimed that a person having ordinary skill in the art before the effective filing date of the claimed invention would expect Tanaka’s device parameters to have at most a different degree compared to those of the claimed invention, rather than having a different kind of operation. A prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. See Warner-Jenkinson Co., Inc. v. Hilton Davis Chemical Co., 520 U.S. 17, 41 USPQ2d 1865 (1997) (under the doctrine of equivalents, a purification process using a pH of 5.0 could infringe a patented purification process requiring a pH of 6.0-9.0) and In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%).
(Re Claim 11) Tanaka teaches the nitride semiconductor device according to claim 2, wherein the first region and the second region exist in a channel region (a channel region extends between source regions and across gate insulation; Fig. 20B markup) of the field effect transistor.
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(Re Claim 12) Tanaka teaches the nitride semiconductor device according to claim 2, but has not been explicitly shown to teach an on state current of the field effect transistor flows from a side of the second principal face of the gallium nitride layer through the first region and the second region to the n type region.
However, as the prior art has been shown to be identical to the claimed structure of the invention, a person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious that Tanaka’s claimed device would also direct on-state current to flow through the claimed path. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). "When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not." See MPEP 2112, particularly 2112.01.
(Re Claim 13) Tanaka teaches the nitride semiconductor device according to claim 2, wherein a peak position (in the center of the Mg concentration sustaining region, as depicted in Fig. 13, that is closest to the region 18 that is closest to the gate insulating film as seen in Fig. 20B; ¶185) exists in the p type region, the peak position being a position where a concentration of p type impurities is the highest in the first direction (maximum concentration is within the Mg concentration sustaining region; Fig. 13, ¶185), wherein the peak position exists in the second region (within the rightmost region 202; ¶185).
(Re Claim 14) Tanaka teaches the nitride semiconductor device according to claim 2, wherein the second region is in contact with the n type region (Fig. 20B).
(Re Claim 15) Tanaka teaches the nitride semiconductor device according to claim 2, wherein the high-concentration region is in contact with the n type region (Fig. 20B).
(Re Claim 17) Tanaka teaches the nitride semiconductor device according to claim 2, wherein the high-concentration region is in contact with the first region (Fig. 20B).
(Re Claim 18) Tanaka teaches the nitride semiconductor device according to claim 2, the field effect transistor further including:
a second electrode (27; Fig. 20B) formed on the side of the second principal face.
Rejection 2/2
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 2, 11, 13-15, and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tanaka et al. (US 2022/0285504).
(Re Claim 2) Tanaka teaches the nitride semiconductor device, comprising: a gallium nitride layer (121+122; Fig. 20B) having a first principal face (10a; Fig. 20B) and a second principal face (10b; Fig. 20B), the second principal face being located on opposite side of the first principal face (Fig. 20B); and a field effect transistor (121+30+20+18+21+23+25; Fig. 20B) formed in the gallium nitride layer, the field effect transistor including:
a gate insulator film (21; Fig. 20B) formed on the gallium nitride layer on a side (topside; Fig 20B) of the first principal face;
a p type region (20+14; Fig. 20B) formed in the gallium nitride layer, the p type region being in contact with the gate insulator film (Fig. 20B);
an n type region (center 18 on the left; Fig. 20B) formed in the gallium nitride layer, the n type region being in contact with the p type region in a first direction (left to right) parallel to an interface (coextensive with contact between left region 14 and gate insulator film 21; Fig. 20B) between the p type region and the gate insulator film; and a first electrode (25 on the left; Fig. 20B) disposed on the side of the first principal face, the first electrode being in contact with the n type region (Fig. 20B), wherein the p type region includes:
a first region (left region 14; Fig. 20B) being in contact with the gate insulator film; and a second region (the region 20 that is to the right of the leftmost 20; Fig. 20B) being in contact with the gate insulator film and lying in the first direction between the first region and the n type region (between the center 18 on the left and the left 14; Fig. 20B), wherein the second region has a higher concentration of p type impurities than the first region (¶154), wherein the field effect transistor further including:
a p type high-concentration region (left 30; Fig. 20B) formed in the gallium nitride layer, the high-concentration region being located between the n type region and the second principal face (Fig. 20B), wherein the high-concentration region has a higher concentration of p type impurities than the first region (¶94) and is in contact with the second region, wherein the concentration of p type impurities in the high-concentration region is 5x1018cm-3 or more but less than 1x1020 cm-3 (¶180), wherein the concentration of p type impurities (within region 201, seen in Fig. 13; ¶141) in the second region is 1x1018 cm-3 or more but less than 5x1018 cm-3 (¶141), and wherein the concentration of p type impurities in the first region is 1x1016 cm-3 or more but less than 1 x1018 cm-3 (¶94).
(Re Claim 11) Tanaka teaches the nitride semiconductor device according to claim 2, wherein the first region and the second region exist in a channel region (a channel region extends between source regions and across gate insulation; Fig. 20B markup) of the field effect transistor.
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(Re Claim 13) Tanaka teaches the nitride semiconductor device according to claim 2, wherein a peak position (in the center of the Mg concentration sustaining region, as depicted in Fig. 13, that is closest to the region 18 that is closest to the gate insulating film as seen in Fig. 20B; ¶185) exists in the p type region, the peak position being a position where a concentration of p type impurities is the highest in the first direction (maximum concentration is within the Mg concentration sustaining region; Fig. 13, ¶185), wherein the peak position exists in the second region (within the rightmost region 202; ¶185).
(Re Claim 14) Tanaka teaches the nitride semiconductor device according to claim 2, wherein the second region is in contact with the n type region (Fig. 20B).
(Re Claim 15) Tanaka teaches the nitride semiconductor device according to claim 2, wherein the high-concentration region is in contact with the n type region (Fig. 20B).
(Re Claim 17) Tanaka teaches the nitride semiconductor device according to claim 2, wherein the high-concentration region is in contact with the first region (Fig. 20B).
(Re Claim 18) Tanaka teaches the nitride semiconductor device according to claim 2, the field effect transistor further including:
a second electrode (27; Fig. 20B) formed on the side of the second principal face.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Tanaka et al. (US 2022/0285504) as applied to claim 2 above.
(Re Claim 12) Tanaka teaches the nitride semiconductor device according to claim 2, but has not been explicitly shown to teach an on state current of the field effect transistor flows from a side of the second principal face of the gallium nitride layer through the first region and the second region to the n type region.
However, as the prior art has been shown to be identical to the claimed structure of the invention, a person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious that Tanaka’s claimed device would also direct on-state current to flow through the claimed path. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). "When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not." See MPEP 2112, particularly 2112.01.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher A Schodde whose telephone number is (571)270-1974. The examiner can normally be reached M-F 1000-1800 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571)272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER A. SCHODDE/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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