CTNF 18/422,867 CTNF 89997 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION This action is responsive to application No. 18422867 filed on 01/25/2024. Information Disclosure Statement Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered. Priority 02-26 AIA Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file. Election/Restrictions 08-25-01 AIA Applicant’s election without traverse of claims 5-24 in the reply filed on 5/12/2026 is acknowledged. Allowable subject matter 12-151-07 AIA 07-97 12-51-07 Claim s 5-14 are allowed. The following is an examiner' s statement of reasons for allowance: Claims 5-14 : The primary reason for the allowance of the claims is the inclusion of the limitation “ wherein the semiconductor gate comprises includes an upper portion and a central portion, the upper portion and the central portion comprising including P-type dopant elements, and the upper portion comprising including oxygen atoms forming a PN junction at the an interface between the central portion and the upper portion” , in all of the claims in combination with the remaining features of independent claim 5. Tipirneni et al. teach a device, comprising: a substrate (Fig. 2I, element 202, paragraph 0025); a barrier layer (Fig. 2I, element 208, paragraph 0026) on the substrate; a gate (Fig. 2I, elements 212-216, paragraph 0027) on the barrier layer, the gate including: a first portion (Fig. 2I, element 212, paragraph 0027) with a first conductivity type; and a second portion (Fig. 2I, element 214, paragraph 0027) with a second conductivity type different from the first conductivity type, the second portion being on a surface of the gate opposite the barrier layer along a first direction (Fig. 2I); and a passivation layer (Fig. 2I, element 222, paragraph 0030) on the barrier layer, on a first sidewall of the gate, and on the surface of the gate. However , Tipirneni et al. do not teach or render obvious the above-quoted features recited in independent claim 5. 07-43 Claims 22-24 are objected to as being dependent upon a rejected base claim (independent claim 21), but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner’s statement of reasons for allowance: The closest prior art known to the Examiner is listed on the PTO 892 forms of record. 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure : Tipirneni et al. (US 2013/0062614) . With respect to dependent claims 22-24, the cited prior art does not anticipate or make obvious, inter alia, the step of: “ wherein the gate includes a third portion covering the first sidewall of the gate and the first surface of the gate, the third portion having the second conductivity type” . Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 15-18, 21 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Tipirneni et al. (US 2013/0062614) . Regarding independent claim 15 , Tipirneni et al. teach a device comprising: PNG media_image1.png 432 847 media_image1.png Greyscale a conductive layer (Fig. 2I, element 204, paragraph 0025); a semiconductor layer (Fig. 2I, element 208, paragraph 0026) having a first surface in contact with the conductive layer and a second surface opposite the first surface of the semiconductor layer; and a gate (Fig. 2I, elements 212-216, paragraph 0027) having a first surface coupled to the second surface of the semiconductor layer, a second surface opposite the first surface of the gate (see annotated figure above), and a first sidewall (see annotated figure above) transverse to the first and second surfaces of the gate, the gate including: a central portion (see annotated figure above, Fig. 2I, element 212, paragraph 0027) with a first conductivity type; an outer layer (see annotated figure above, Fig. 2I, element 214, paragraph 0027) with a second conductivity type opposite the first conductivity type at the second surface of the gate; and a peripheral layer (see annotated figure above, Fig. 2I, element 214, paragraph 0027, note that the claim language does not require the outer layer and peripheral layer to be separate and distinct layers) with the second conductivity type at the first sidewall of the gate. Regarding claim 16 , Tipirneni et al. teach wherein the gate has a P-type doping and the outer and peripheral layers have an N-type doping (paragraph 0027). Regarding claim 17 , Tipirneni et al. teach comprising a PN junction at an interface between the central portion of the gate and the peripheral and outer layers of the gate (Fig. 2I, paragraph 0027). Regarding claim 18 , Tipirneni et al. teach comprising a passivation layer (Fig. 2I, element 222, paragraph 0030) on the second surface of the semiconductor layer, the peripheral layer of the gate, and the outer layer of the gate. Regarding independent claim 21 , Tipirneni et al. teach a device, comprising: a substrate (Fig. 2I, element 202, paragraph 0025); a barrier layer (Fig. 2I, element 208, paragraph 0026) on the substrate; a gate (Fig. 2I, elements 212-216, paragraph 0027) on the barrier layer, the gate including: a first portion (Fig. 2I, element 212, paragraph 0027) with a first conductivity type; and a second portion (Fig. 2I, element 214, paragraph 0027) with a second conductivity type different from the first conductivity type, the second portion being on a surface of the gate opposite the barrier layer along a first direction (Fig. 2I); and a passivation layer (Fig. 2I, element 222, paragraph 0030) on the barrier layer, on a first sidewall of the gate, and on the surface of the gate . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tipirneni et al. (US 2013/0062614) in view of Chou (US 2024/0105780) . Regarding claim 19, Tipirneni et al. teach all of the limitations as discussed above. Tipirneni et al. do not explicitly teach comprising a gap in the passivation layer on the outer layer of the gate and a gate contact metallization directly coupled to the gate through the gap. Chou teach a HEMT device comprising a gap (Fig. 1) in the passivation layer (Fig. 1, element 40, paragraph 0031) on the outer layer of the gate (Fig. 1, element 302, paragraph 0076) and a gate contact (Fig. 1, element 52, paragraph 0031) metallization directly coupled to the gate through the gap. It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Tipirneni et al. according to the teachings of Chou with the motivation to provide interconnection. Regarding claim 20, Tipirneni et al. modified by Chou teach comprising an insulating layer (Fig. 1, element 50, paragraph 0087 of Chou) entirely covering the passivation layer and including a portion between the gate contact metallization and the outer layer of the gate (Fig. 2I of Tipirneni and Fig. 1 of Chou). Cited Prior Art The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHED AHMED whose telephone number is (571)272-3477. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached on 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHAHED AHMED/ Primary Examiner, Art Unit 2813 Application/Control Number: 18/422,867 Page 2 Art Unit: 2813 Application/Control Number: 18/422,867 Page 3 Art Unit: 2813 Application/Control Number: 18/422,867 Page 4 Art Unit: 2813 Application/Control Number: 18/422,867 Page 5 Art Unit: 2813 Application/Control Number: 18/422,867 Page 6 Art Unit: 2813 Application/Control Number: 18/422,867 Page 7 Art Unit: 2813 Application/Control Number: 18/422,867 Page 8 Art Unit: 2813 Application/Control Number: 18/422,867 Page 9 Art Unit: 2813
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