DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species I Modification I in the reply filed on 6/30/2026 is acknowledged. The traversal is on the ground(s) that it should be no undue burden on the examiner to consider all claims in the single application. This is not found persuasive because the search to find art teaching a P-N junction diode is different from the search to find a P-I-N junction diode. Furthermore, the search strategies for first and second semiconductor blocks arranged parallel or perpendicular to the direction of the source electro, gate electrode, and drain electrode will be different.
The requirement is still deemed proper and is therefore made FINAL.
Claims 4 and 8 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 6/30/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 7, 9-10, 17, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. US 20190096879 A1 (hereinafter referred to as Chen).
Regarding claim 1, Chen teaches
A semiconductor device (“semiconductor device 6” para. 0052 FIG. 6), comprising:
a substrate (“substrate 100” para. 0052);
a channel layer (“channel layer 104” para. 0052) disposed on the substrate;
a barrier layer (“barrier layer 106” para. 0052) disposed on the channel layer;
a gate electrode (“gate G” para. 0052) disposed on the barrier layer;
a dielectric layer (“dielectric layer 108” para. 0052) disposed on the gate electrode;
a source electrode (“source S” para. 0052) and a drain electrode (“drain D” para. 0052) disposed on opposite sides of the gate electrode, respectively, and in contact with the channel layer, respectively (“source S” and “drain D” are in contact with “channel layer 104” as shown in FIG. 6);
a diode structure (“P-N junction diode 20a” in “substrate 100”, para. 0052) disposed on the dielectric layer and electrically connected to the source electrode (“diode 20a” is on a lower side of “dielectric layer 108” and in electrical contact with “source S” through “first conductive via 110”, para. 0054).
Regarding claim 2, Chen teaches the semiconductor device as claimed in claim 1, wherein the diode structure and the gate electrode at least partially overlap in a normal direction of the substrate (“gate G” and “diode 20a” partially overlap in a normal direction of “substrate 100”).
Regarding claim 3, Chen teaches the semiconductor device as claimed in claim 1, wherein the diode structure further comprises: a first semiconductor block (“first region 100a” para. 0054) having a first conductivity type (“first region 100a” is of a first conductivity type, para. 0027) and electrically connected to the source electrode (“first region 100a” connects to “source S” through “first conductive via 110”); and
a second semiconductor block (“second region 100b” para. 0054) having a second conductivity type different from the first conductivity type (“second region 100b” is of a first conductivity type, para. 0027), in contact with the first semiconductor block, and electrically connected to the barrier layer, the channel layer, or the drain electrode (“second region 100b” is electrically connected to “drain D” through “second conductive via 120”, para. 0054).
Regarding claim 7, Chen teaches the semiconductor device as claimed in claim 3, wherein the source electrode, the gate electrode, and the drain electrode are arranged along a first direction (“source S”, “gate G”, and “drain D” are arranged horizontally along FIG. 6), and the first semiconductor block and the second semiconductor block are arranged along the first direction (“first region 100a” and “second region 100b” are arranged horizontally along FIG. 6).
Regarding claim 9, Chen teaches the semiconductor device as claimed in claim 3, wherein the first conductivity type is P-type, and the second conductivity type is N-type (“first region 100a” is of a first conductive type and “second region 100b” is of a second conductive type, and “when the first conductive type is a P-type, the second conductive type is an N-type”, para. 0027).
Regarding claim 10, Chen teaches the semiconductor device as claimed in claim 1, wherein the diode structure is a P-N junction diode, a P-I-N diode, a Schottky diode, or a combination thereof (“P-N junction diode 20a” is a P-N junction diode, para. 0037).
Regarding claim 17, Chen teaches the semiconductor device as claimed in claim 1, wherein a projection of the diode structure on the substrate at least partially overlaps a projection of the gate electrode on the substrate (“gate G” and “diode 20a” partially overlap in a normal direction of “substrate 100”).
Regarding claim 19, Chen teaches the semiconductor device as claimed in claim 1, further comprising: a compound semiconductor layer disposed between the barrier layer and the gate electrode (“dielectric layer 118” is between “barrier layer 106” and “gate G” as is made of SiN, such that it is considered a compound semiconductor based on its composition, para. 0052).
Regarding claim 20, Chen teaches the semiconductor device as claimed in claim 1, further comprising: a buffer layer (“buffer layer 102” para. 0054 FIG. 6) disposed between the substrate and the channel layer.
Claims 1 and 12-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al. US 20210408273 A1 (hereinafter referred to as Wu)
Regarding claim 1, Wu teaches
A semiconductor device (“single high-voltage hybrid III-N device 100” para. 0035 FIG. 2A), comprising:
a substrate (“substrate 14” para. 0036);
a channel layer (“III-N channel layer 16” para. 0038) disposed on the substrate;
a barrier layer (“III-N barrier layer 17” para. 0038) disposed on the channel layer;
a gate electrode (“gate electrode 135” para. 0042) disposed on the barrier layer;
a dielectric layer (“insulator layer 18” para. 0042) disposed on the gate electrode;
a source electrode (“source electrode 134” para. 0041) and a drain electrode (“drain electrode 136” para. 0041) disposed on opposite sides of the gate electrode, respectively, and in contact with the channel layer, respectively (“source electrode 134” and “drain electrode 136” are at opposite sides of “gate electrode 135” and in contact with “III-N channel layer 16”);
a diode structure (“E-mode device 122” has an intrinsic body diode represented as “diode 37” in FIG. 4, para. 0049) disposed on the dielectric layer and electrically connected to the source electrode (“E-mode device 122” is electrically connected to “source electrode 134”, para. 0045).
Regarding claim 12, Wu teaches the semiconductor device as claimed in claim 1, wherein the diode structure is closer to the source electrode than to the drain electrode (“E-mode device 122” is shown overlapping “source electrode 134” and further away to “drain electrode 136”).
Regarding claim 13, Wu teaches the semiconductor device as claimed in claim 1, further comprising: a source field plate (“source pad 137” para. 0045) disposed on the dielectric layer, between the source electrode and the drain electrode, and electrically connected to the source electrode (“source pad 137” partially extends between “source electrode 134” and “drain electrode 136”, and is electrically connected to “source electrode 134”, para. 0045).
Regarding claim 14, Wu teaches wherein the source field plate is disposed between the diode structure and the gate electrode (“source pad 137” is partially between “E-mode device 122” that includes “diode 37” and “gate electrode 135”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 1 above.
Chen teaches the semiconductor device as claimed in claim 1 but fails to teach wherein the diode structure is formed by an epitaxial process or a furnace process.
Nevertheless, the language, term, or phrase " the diode structure is formed by an epitaxial process or a furnace process," is directed towards the process of making a diode structure. It is well settled that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language " the diode structure is formed by an epitaxial process or a furnace process " only requires a diode structure, which does not distinguish the invention from Chen, who teaches the structure as claimed.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 1 above, in view of Han et al. US 5907181 A (hereinafter referred to as Han).
Regarding claim 5, Chen teaches the semiconductor device as claimed in claim 3 but fails to teach wherein the diode structure further comprises: a first doped region disposed on the dielectric layer, in contact with the first semiconductor block, and having the first conductivity type; and a second doped region disposed on the dielectric layer, in contact with the second semiconductor block, and having the second conductivity type.
Nevertheless, Han teaches a P-N junction diode comprising “conductive contact M2”, “heavily doped N.sup.+ region 3'”, substrate 3” including an N-type dopant, “P.sup.- region 5”, “P.sup.+ region 6” and “conductive contact M3” arranged in that order (col 3 lines 58-61, col 4 lines 13-14, col 4 lines 23-28 FIG. 5). The heavily doped “N.sup.+ region 3'” has been added to provide an ohmic contact for the conductive contact M2” and the “P.sup.+ region 6” provides an ohmic contact for the “conductive contact M3” (col 4 lines 25-28). Furthermore, “P.sup.+ region 6” may reduce a leakage current when a reverse biased voltage is applied to the diode (col 5 lines 6-8). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that higher doped regions such as “N.sup.+ region 3'” and “P.sup.+ region 6” can provide contact with “first conductive via 110” and “second conductive via 120” with reduced resistance and reduce the leakage current when in reverse bias.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught in Chen with the doping profile of the diode shown in Han. First and second doped regions in contact with the first and second semiconductor blocks, respectively, serve as contact regions that form ohmic contacts with metals. When in reverse bias, the first doped region can reduce the leakage current.
Regarding claim 6, Chen, modified by Han, teaches the semiconductor device as claimed in claim 5, wherein a doping concentration of the first doped region is greater than a doping concentration of the first semiconductor block (“P.sup.+ region 6” is described as having a relatively high dopant concentration and is understood to be greater than in “P.sup.- region 5”), and a doping concentration of the second doped region is greater than a doping concentration of the second semiconductor block (“N.sup.+ region 3” is described as heavily doped and is understood to have a greater concentration that N-type doped “substrate 3).
Claim 13 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 1 above, in view of Simin et al. US 20140077311 A1 (hereinafter referred to as Simin).
Regarding claim 13, Chen teaches the semiconductor device as claimed in claim 1 but fails to teach further comprising: a source field plate disposed on the dielectric layer, between the source electrode and the drain electrode, and electrically connected to the source electrode.
Nevertheless, Simin teaches
a source field plate (“source surface structure 54A” which is a field plate, para. 0032 FIG. 4C) disposed on the dielectric layer (“isolation layer 56” para. 0032), between the source electrode (“source contact 42” para. 0032) and the drain electrode (“drain contact 44” para. 0032), and electrically connected to the source electrode (source surface structure 54A” is connected to “source contact 42”).
Chen and Simin teach HEMT devices. “Field plate “surface structures 54A, 54B can reduce electric filed non-uniformities at the edges of the source contact 42 and drain contact 44, respectively” (para. 0032). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that a field plate “source surface structure 54A” can control the uniformity of the electric field around the “source S”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device in Chen with the source field plate taught in Simin. A source field plate can reduce electric field non-uniformities around the source electrode.
Regarding claim 15, Chen, modified by Simin, teaches the semiconductor device as claimed in claim 13, wherein a projection of the diode structure on the substrate is located within a projection of the source field plate on the substrate (“source surface structure 54A” formed on “semiconductor device 6” of Chen will overlap the “P-N junction diode 20a”).
Regarding claim 16, Chen, modified by Simin, teaches the semiconductor device as claimed in claim 13, wherein a projection of the gate electrode on the substrate is located within a projection of the source field plate on the substrate (“source surface structure 54A” is shown overlapping “gate 46” in FIG. 4C, para. 0032).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 1 above, in view of Chen et al. US 20140014967 A1 (hereinafter referred to as Chen’967) and Teplik et al. US 20140061659 A1 (hereinafter referred to as Teplik).
Chen teaches the semiconductor device as claimed in claim 1, wherein the diode structure comprises silicon (“substrate 100” comprises silicon, para. 0021).
However, Chen fails to teach wherein the diode structure comprises polysilicon.
Nevertheless, Chen’967 teaches a “substrate 102” upon which a Group-III nitride HEMT device is formed (para. 0009, 0019-0020). “Substrate 102” may comprise amorphous silicon, polysilicon, or other materials (para. 0010). As noted in Teplik et al. US 20140061659 A1, the choice of material can be determined based on thermal and electrical properties, as well as manufacturing costs (para. 0018). “P-N junction dide 20a” in Chen is formed in a silicon “substrate 100” (para. 0021). The examiner understands that polysilicon can be doped as desired. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that polysilicon is a known material suitable for use as a substrate and can be chosen based on desired properties and cost.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught in Chen with the polysilicon substrate as taught in Chen’967 and Teplik. Polysilicon is a known material suitable for use as a substrate in which a diode can be formed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC MULERO FLORES whose telephone number is (571)270-0070. The examiner can normally be reached Mon-Fri 8am-5pm (typically).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC MANUEL MULERO FLORES/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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