DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species I directing to claims 1-15, in the reply filed on August 31, 2026, is acknowledged. The traversal is on the ground(s) that “Species II is Species I plus one added rail in the same metal layer, in the same art unit and classification. The Species Il search is a subset of, not a different field from, the Species I search. Examining claim 1 already requires searching art with internal rails, since claim 1 reads on them.”. This is not found persuasive because; the species I and II are patentably distinct as claims 1 and 10 do not require (i)an internal rail in the first front wiring layer; (ii) a second front side front side wiring layer connected to the internal rail and claim 19 does not require all the limitations of claim 1 or claim 10 in the same combination. Claim 19 is an independent claim drawn to a standard sell and not a dependent claim that merely adds an optional feature to Claim 1. The presence of mutually exclusive claim set satisfies the distinguished species test.
Furthermore, the inventions require a different field of search (e.g., searching for different CPC groups/subgroups or electronic resources, or employing different search strategies or search queries). They require different keyword searches. Furthermore, Species I need searching in H10W20/427, H10W20/481 and H10W20/40, Species II additionally needs H10D89/10. Moreover, a search for backside power rail and front side power rail does not find art pertinent to internal rail or local rail. That is a serious burden under MPEP § 808.02.
The requirement is still deemed proper and is therefore made FINAL.
Claims 19-23 are withdrawn as non-elected species. Claims 16-18 and 24-29 have been canceled. Currently claims 1-15 and 19-23 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/25/2024 and 07/16/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner and made of record.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9, line 4 missing the preposition in front of “the first direction”. There is insufficient antecedent basis for these limitations in the claim.
Appropriate correction needed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 10-12 and 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Huang; Yu-Xuan (US 20240008243 A1) “Huang et al.”.
Regarding Independent Claim 1, Huang et al. Figs. 4A-4B, 5-9 discloses, an integrated circuit (“a semiconductor device 100” ¶ [0026]) comprising:
a power rail (“The metal layer M0 may include several electrically separated metal lines that, despite being on substantially the same layer, are used to distribute voltages Vdd1” ¶ [0033]) extending in a first direction and configured to receive a supply voltage (“the metal layer M0 includes two metal lines extending in the X-direction distributing the voltage Vdd1” ¶ [0033]);
a gate line below the power rail and extending in a second direction that intersects the first direction (“the gates GT extend in the Y-direction and are evenly spaced from each other along the X-direction.” ¶ [0031]);
a source/drain region adjacent to the gate line (“Source/drain (S/D) regions are formed in the diffusion region RX and interpose adjacent gates GT. In some embodiments, source/drain regions are formed of doped epitaxial features.” ¶ [0046]) in the first direction (“a plurality of active regions formed on a substate, each of the active regions extending lengthwise in a first direction,” ¶ [0054]) and configured to receive the supply voltage from the power rail (“the top metal line provides the voltage Vdd1 to the source/drain regions of the FETs in the cell C1 and the source/drain regions of some of the FETs in the cell C2 through vias Via-v1;” ¶ [0033]);
a frontside wiring layer above the power rail, connected to the power rail, and configured to transmit the supply voltage to the power rail (“Not depicted in FIG. 4A, there may be other metal layers (e.g., M1, M2, . . . Mx) suspended above the metal layer M0, such as a total of four to ten metal layers. These metal layers form a frontside power rail to supply voltages from the voltage domain Vdd1 to the semiconductor device 100” ¶ [0033]; “the package bumps 120 may be deposited on the frontside of the semiconductor device 100. Accordingly, the voltages from different voltage domains are passed to the frontside power rail from the package bumps 120, and some of the voltages are further passed to the backside power rail from the frontside power rail through power taps that extend through the substrate.” ¶ [0045]); and
a backside wiring layer below the power rail, connected to the power rail, and configured to transmit the supply voltage to the power rail (“to pass the voltage Vdd1 to the frontside power rail from the backside power rail, a conductive path is provided between the backside metal line in BM0 and the frontside metal line in M0. The conductive path includes a backside via VB-v1, a source/drain region contacting the backside via VB-v1, a source/drain contact MD contacting the source/drain region, and a frontside via Via-v1 contacting the source/drain contact MD. The conductive path is also referred to as a power tap.” ¶ [0047]).
Regarding Claim 2, Huang et al. discloses the limitations of claim 1. Huang et al. Figs. 4A-4B, 5-9 further discloses, further comprising a backside (“The metal lines are electrically connected to the metal MD by backside vias” ¶ [0037]),
wherein the backside wiring layer is connected to the power rail through the backside via (“a conductive path is provided between the backside metal line in BM0 and the frontside metal line in M0. The conductive path includes a backside via VB-v1” ¶ [0047]).
Regarding Claim 3, Huang et al. discloses the limitations of claim 2. Huang et al. Figs. 4A-4B, 5-10 further discloses, further comprising:
a contact (“The metal MD and metal M0 are electrically conductive and may be made of other types of conductive materials despite being named “metal.” The metal MD may serve as local interconnects, such as source/drain contacts.” ¶ [0032]) extending in the vertical direction on the backside via (“The depicted power tap includes the backside via VB-v1, a metal MD contacting the backside via VB-v1, and a frontside via Via-v1 contacting the metal MD. The metal MD extends through the substrate. In some embodiments, the metal MD is a through-substrate via (TSV)” ¶ [0049]); and
a contact via on the contact (“a frontside via Via-v1 contacting the metal MD” ¶ [0049]),
wherein the backside wiring layer is connected to the power rail through the backside via, the contact, and the contact via (“The depicted power tap includes the backside via VB-v1, a metal MD contacting the backside via VB-v1, and a frontside via Via-v1 contacting the metal MD. The metal MD extends through the substrate. In some embodiments, the metal MD is a through-substrate via (TSV).” ¶ [0051]).
Regarding Independent Claim 10, Huang et al. Figs. 4A-4B, 5-9 discloses, an integrated circuit (“a semiconductor device 100” ¶ [0026]) comprising:
a source region (“Source/drain (S/D) regions are formed in the diffusion region RX and interpose adjacent gates GT. In some embodiments, source/drain regions are formed of doped epitaxial features.” ¶ [0046]);
a drain region (“Source/drain (S/D) regions are formed in the diffusion region RX and interpose adjacent gates GT. In some embodiments, source/drain regions are formed of doped epitaxial features.” ¶ [0046]) spaced apart from the source region in a first direction (“a plurality of active regions formed on a substate, each of the active regions extending lengthwise in a first direction,” ¶ [0054]);
a gate line between the source region and the drain region, the gate line extending in a second direction that intersects to the first direction (“the gates GT extend in the Y-direction and are evenly spaced from each other along the X-direction.” ¶ [0031]);
a frontside wiring layer above the gate line (“metal layer M0 may include several electrically separated metal lines that, despite being on substantially the same layer, … there may be other metal layers (e.g., M1, M2, . . . Mx) suspended above the metal layer M0, such as a total of four to ten metal layers.” ¶ [0033]); and
a backside wiring layer below the gate line (“backside metal layer BM0 may exist on the backside of the semiconductor device 100. The backside metal layer BM0 exists on a layer vertically separated from the backside surface of the substrate. e.g., below the backside surface. …Not depicted in FIG. 4B, there may be other backside metal layers (e.g., BM1, BM2, . . . BMy) suspended underneath the backside metal layer BM0, such as a total of two to four backside metal layers.” ¶ [0037),
wherein the frontside wiring layer comprises a first frontside wiring pattern extending in the first direction (“FIG. 4A, the metal layer M0 includes two metal lines extending in the X-direction distributing the voltage Vdd1” ¶ [0033]), connected to the source region, and configured to transmit a supply voltage to the source region (“the top metal line provides the voltage Vdd1 to the source/drain regions of the FETs in the cell C1 and the source/drain regions of some of the FETs in the cell C2 through vias Via-v1;” ¶ [0033]), and
wherein the backside wiring layer comprises a first backside wiring pattern connected to the source region and configured to transmit the supply voltage to the source region (“In the embodiment illustrated in FIG. 4B, the backside metal layer BM0 includes two metal lines extending in the X-direction distributing the voltage Vdd2 and two metal line therebetween distributing the voltage Vss. The metal lines are electrically connected to the metal MD by backside vias. In the illustrated embodiment, the topmost metal line provides the voltage Vdd2 to the source/drain regions of the FETs in the cell C3 and the source/drain regions of some of the FETs in the cell C2 through vias VB-v2; the bottom metal line provides the voltage Vdd2 to the source/drain regions of the FETs in the cell C3′ and the source/drain regions of some of the FETs in the cell C2′ through vias VB-v2; and the middle two metal lines provide the voltage Vss to the source/drain regions of the FETs in the top row of cells C1-C3 and the bottom row of cells C1′-C3′ through vias VB-g, respectively” ¶ [0037]).
Regarding Claim 11, Huang et al. discloses the limitations of claim 10. Huang et al. Figs. 4A-4B, 5-9 further discloses, further comprising a backside via, on the backside wiring layer (“The metal lines are electrically connected to the metal MD by backside vias” ¶ [0037]),
wherein the backside wiring layer is connected to the source region through the backside via (“a source/drain region contacting the backside via VB-v1” ¶ [0047]).
Regarding Claim 12, Huang et al. discloses the limitations of claim 10. Huang et al. Figs. 4A-4B, 5-9 further discloses, further comprising:
a contact on the source region (“On the source region 262A along the Z-direction, the MD region 265A is formed.” ¶ [0043]); and
a contact via on the contact (“The metal MD and metal M0 are electrically conductive and may be made of other types of conductive materials despite being named “metal.” The metal MD may serve as local interconnects, such as source/drain contacts.” ¶ [0032]; “a source/drain contact MD contacting the source/drain region” ¶ [0047]),
wherein the frontside wiring pattern is connected to the source region through the contact via (“the metal layer M0 includes two metal lines extending in the X-direction distributing the voltage Vdd1 and one metal line therebetween distributing the voltage Vss. The metal lines are electrically connected to the metal MD by vias. In the illustrated embodiment, the top metal line provides the voltage Vdd1 to the source/drain regions of the FETs in the cell C1 and the source/drain regions of some of the FETs in the cell C2 through vias Via-v1; the bottom metal line provides the voltage Vdd1 to the source/drain regions of the FETs in the cell C1′ and the source/drain regions of some of the FETs in the cell C2′ through vias Via-v1; and the middle metal line is shared by the cells in the top and bottom rows to provide the voltage Vss to the source/drain regions of the FETs in the cells C1-C3 and C1′-C3′ through vias Via-g. ¶ [0033]).
Regarding Claim 15, Huang et al. discloses the limitations of claim 10. Huang et al. Figs. 4A-4B, 5-9 further discloses, wherein the backside wiring layer further comprises a second backside wiring pattern (“In the embodiment illustrated in FIG. 4B, the backside metal layer BM0 includes two metal lines extending in the X-direction distributing the voltage Vdd2 and two metal line therebetween distributing the voltage Vss” ¶ [0037]),
wherein the first backside wiring pattern is configured to receive a first voltage (“The power taps may directly land on the backside metal line in the BM0 layer carrying Vdd1” ¶ [0050]), and
wherein the second backside wiring pattern is configured to receive a second voltage (“In the embodiment illustrated in FIG. 4B, the backside metal layer BM0 includes two metal lines extending in the X-direction distributing the voltage Vdd2 and two metal line therebetween distributing the voltage Vss” ¶ [0037]; “backside metal line in the BM0 layer carrying Vdd2 is divided into two segments, one still carrying Vdd2 and another one carrying Vdd1.” ¶ [0050]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Huang; Yu-Xuan (US 20240008243 A1) “Huang et al.” in view of Peng; Shih-Wei (US 20210391318 A1) “Peng et al.”.
Regarding Claim 4, Huang et al. discloses the limitations of claim 1. Huang et al. Figs. 4A-4B, 5-9 further discloses, “there may be other metal layers (e.g., M1, M2, . . . Mx) suspended above the metal layer M0, such as a total of four to ten metal layers.” (Huang et al. ¶ [0033])
However, Huang et al. does not disclose further comprising a power rail via on the power rail,
wherein the frontside wiring layer is connected to the power rail through the power rail via.
In the similar field of endeavor of IC devices, Peng et al. Figs. 1-9 discloses further comprising a power rail via on the power rail (“a contact layer VD including a via contact 275 can be formed according to the layout pattern 175. Above the contact layer VD along the Z-direction, a front side metal layer M0 including a front side metal rail 270” ¶ [0042]),
wherein the frontside wiring layer is connected to the power rail through the power rail via (“The front side metal rails may be electrically connected to the transistor (e.g., source region, drain region, or gate region) through via contacts formed according to the layout patterns 175, 180”; “In some embodiments, the integrated circuit formed according to the layout patterns shown in FIGS. 1A-1C includes additional layers (e.g. M1-M7) for front side metal rails.” ¶ [0039]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the IC structure of Huang et al. with the power rail via of Peng et al. in order to allow a reduction in a number of front side metal rails and via connections, such that an area of the integrated circuit can be reduced (Peng et al. ¶ [0048].
Regarding Claim 13, Huang et al. discloses the limitations of claim 10.
However, Huang et al. does not disclose, wherein the frontside wiring layer further comprises a second frontside wiring pattern connected to the drain region and extending in the first direction
In the similar field of endeavor of IC devices, Peng et al. Figs. 1-9 discloses, wherein the frontside wiring layer further comprises a second frontside wiring pattern connected to the drain region and extending in the first direction (“the metal rail formed according to the layout pattern 170A can be electrically coupled to the drain region of the P-type transistor through the MD region formed according to the layout pattern 165B and the via contact formed according to the layout pattern 175” ¶ [0039]; “the drain region 262B is electrically coupled to the front side metal rail 270 through the via contact 275 and the MD region 265B,” ¶ [0046]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to orient Huang’s backside power lines in the second direction and to space the supply line from the ground line along the first direction as described in Peng et al. in order to provide further flexibility in placement and routing, and allows an integrated circuit to be designed in a compact form (Peng et al. ¶ [0057]).
Claims 5 is rejected under 35 U.S.C. 103 as being unpatentable over Huang; Yu-Xuan (US 20240008243 A1) “Huang et al.” in view of CHEN; Chih-Liang (US 20230036522 A1) “CHEN et al.”.
Regarding Claim 5, Huang et al. discloses the limitations of claim 1. However, Huang et al. does not disclose wherein the frontside wiring pattern at least partially overlaps the backside wiring pattern.
In the similar field of endeavor of IC Devices, CHEN et al. Figs. 1-5 discloses wherein the frontside wiring pattern at least partially overlaps the backside wiring pattern (“front-side power rail 30F extending in the X-direction is in a front-side conductive layer. The back-side power rail 30B extending in the X-direction is in a back-side conductive layer” ¶ [0047]; Figs. 1C,2C 5C shows the frontside wiring pattern at least partially overlaps the backside wiring pattern).
It would have been obvious to person having ordinary skill in the art before the effective filling date to orient Huang’s wiring patterns as described in CHEN et al. in order to reduce the stray capacitive couplings between the front-side signal lines in the neighboring IC cells. (CHEN et al. ¶ [0109]).
Claims 14 is rejected under 35 U.S.C. 103 as being unpatentable over Huang; Yu-Xuan (US 20240008243 A1) “Huang et al.” in view of Peng; Shih-Wei (US 20210391318 A1) “Peng et al.” further in view of CHEN; Chih-Liang (US 20230036522 A1) “CHEN et al.”.
Regarding Claim 14, Huang et al. discloses the limitations of claim 13. However, Huang et al. does not disclose, wherein the second frontside wiring pattern at least partially overlaps the first backside wiring pattern.
In the similar field of endeavor of IC Devices, CHEN et al. Figs. 1-5 discloses wherein the second frontside wiring pattern at least partially overlaps the first backside wiring pattern (“front-side power rail 30F extending in the X-direction is in a front-side conductive layer. The back-side power rail 30B extending in the X-direction is in a back-side conductive layer” ¶ [0047]; Figs. 1C,2C 5C shows the frontside wiring pattern at least partially overlaps the backside wiring pattern).
It would have been obvious to person having ordinary skill in the art before the effective filling date to orient Huang’s wiring patterns as described in CHEN et al. in order to reduce the stray capacitive couplings between the front-side signal lines in the neighboring IC cells. (CHEN et al. ¶ [0109]).
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Huang; Yu-Xuan (US 20240008243 A1) “Huang et al.” in view of Chen; Andy Wangkun (US 20220084561 A1) “Chen-1”.
Regarding Claim 6, Huang et al. discloses the limitations of claim 1. Huang et al. Figs. 4A-4B, 5-9 further discloses, wherein the supply voltage comprises a first voltage and a second voltage (“In the embodiment illustrated in FIG. 4A, the metal layer M0 includes two metal lines extending in the X-direction distributing the voltage Vdd1 and one metal line therebetween distributing the voltage Vss” ¶ [0033]),
wherein the power rail comprises:
a first power rail configured to receive the first voltage (“the frontside power rail includes a first frontside metal line providing the first power supply voltage” ¶ [0053]); and
a second power rail configured to receive the second voltage (“a second frontside metal line parallel to the first frontside metal line and providing a ground reference voltage” ¶ [0053]),
wherein the source/drain region comprises:
a first source/drain region configured to receive the first voltage (“the top metal line provides the voltage Vdd1 to the source/drain regions of the FETs in the cell C1 and the source/drain regions of some of the FETs in the cell C2 through vias Via-v1” ¶ [0033]); and
a second source/drain region configured to receive the second voltage (“to provide the voltage Vss to the source/drain regions of the FETs in the cells C1-C3 and C1′-C3′ through vias Via-g.” ¶ [0033]),
wherein the frontside wiring layer comprises:
a first frontside wiring pattern (Vdd1 line of the higher frontside metal layers (e.g., M1, M2, . . . Mx) in Fig. 4A) connected to the first power rail and configured to transmit the first voltage to the first power rail (“These metal layers form a frontside power rail to supply voltages from the voltage domain Vdd1 to the semiconductor device 100.” ¶ [0033]); and
wherein the backside wiring layer comprises:
a first backside wiring pattern connected to the first power rail and configured to transmit the first voltage to the first power rail (“there may be other backside metal layers (e.g., BM1, BM2, . . . BMy) suspended underneath the backside metal layer BM0, such as a total of two to four backside metal layers. These metal layers form a backside power rail to supply voltages from the voltage domain Vdd2 to the semiconductor device 100.” ¶ [0037]); and
a second backside wiring pattern electrically connected to the second power rail and configured to transmit the second voltage to the second power rail (“the frontside metal lines and backside metal lines providing Vss are actually electrically connected. That is, the frontside vias and backside vias help distribution of the voltage VSS to both the frontside and backside of the semiconductor device 100.” ¶ [0038]).
However, Huang does not disclose a second frontside wiring pattern connected to the second power rail and configured to transmit the second voltage to the second power rail.
In the similar field of endeavor of IC devices, Chen-1 Fig. 1-2 discloses a second frontside wiring pattern (“a frontside power network (FSPN) 108 configured for memory architecture, such as, e.g., backside power for memory control circuitry. In some instances, the frontside power network (FSPN) 108 may include frontside metal layers that supply a core voltage in multiple voltage domains, wherein the one or more voltage domains of the core voltage may refer to an internal core voltage domain (VDDC) and/or an external core voltage domain (VDDCE).” ¶ [0013]) connected to the second power rail and configured to transmit the second voltage to the second power rail (“portions of the power rails (R1-R2) may be coupled to different power supplies in different power domains. For instance, as shown in FIG. 2, portions of the power rails (R1-R2) may be used to couple FS metal (M0) and BS metal (BM0) to ground, such as, e.g., external ground (VSSE). Also, as shown in FIG. 2, other portions of the power rails (R1-R2) may be used to couple the frontside metal (M0) and the backside metal (BM0) to various different periphery domains, such as, e.g., the internal and external periphery domains (VDDP, VDDPE).” ¶ [0029]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify front side metal layers of Huang et al. as with the teaching of Chen-1 in order to improve current-resistance (IR) drop, performance, and area of memory control circuitry (Chen-1, ¶ [0032]).
Regarding Claim 7, Huang et al. discloses the limitations of claim 6. Huang et al. Figs. 4A-4B, 5-9 further discloses, wherein each of the first backside wiring pattern and the second backside wiring pattern extends in the first direction (“In the embodiment illustrated in FIG. 4B, the backside metal layer BM0 includes two metal lines extending in the X-direction distributing the voltage Vdd2 and two metal line therebetween distributing the voltage Vss.” ¶ [0037]).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Huang; Yu-Xuan (US 20240008243 A1) “Huang et al.” in view of Chen; Andy Wangkun (US 20220084561 A1) “Chen-1” further in view of Peng; Shih-Wei (US 20210391318 A1) “Peng et al.”
Regarding Claim 8, Huang et al. discloses the limitations of claim 6. However, Huang et al. does not disclose, wherein each of the first backside wiring pattern and the second backside wiring pattern extends in the second direction, and
wherein each of the first backside wiring pattern and the second backside wiring pattern is arranged in a line in the second direction.
In the similar field of endeavor of IC devices, Peng et al. Figs. 4A-4B and 7 discloses, wherein each of the first backside wiring pattern and the second backside wiring pattern extends in the second direction (“layout patterns 640A-640D for backside metal rails in M−1 layer may extend in the X-direction, while layout patterns 710A-710E for backside metal rails in M−2 layer may extend in the Y-direction.” ¶ [0057]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to orient Huang’s backside power lines in the second direction and to space the supply line from the ground line along the first direction as described in Peng et al. in order to provide further flexibility in placement and routing, and allows an integrated circuit to be designed in a compact form (Peng et al. ¶ [0057]).
However, Peng et al. does not disclose wherein each of the first backside wiring pattern and the second backside wiring pattern is arranged in a line in the second direction.
In the similar field of endeavor of IC devices, Chen-1 Fig. 2 discloses wherein each of the first backside wiring pattern and the second backside wiring pattern is arranged in a line in the second direction (“at least one first backside power rail may be configured with one or more rail breaks (RB) that interrupt continuity so as to thereby allow at least one second backside power rail in the second region 214 to supply the periphery voltage (VDDP) to the control logic”; “The rail break (RB) may provide a spatial opening in the at least one first backside power rail to allow coupling of the at least one second backside power rail to the control logic.” ¶ [0030]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to combine the teachings Huang et al. as modified by Peng et al with the teaching of Chen-1 in order to allow at least one second backside power rail to supply the periphery voltage to the control logic. Also, in some instances, the continuity break may provide a spatial opening so as to thereby allow coupling of the at least one second backside power rail to the memory control circuitry (Chen-1, ¶ [0008]).
Regarding Claim 9, Huang et al. discloses the limitations of claim 6. Huang et al. further discloses, wherein the first backside wiring pattern is spaced apart from the second backside wiring pattern in the first direction (Fig. 4B BM0 lines distributing Vdd2 and Vss respectively).
However, Huang et al. does not disclose, wherein each of the first backside wiring pattern and the second backside wiring pattern extends in the second direction,
In the similar field of endeavor of IC devices, Peng et al. Figs. 1-9 discloses, wherein each of the first backside wiring pattern and the second backside wiring pattern extends in the second direction (“layout patterns 640A-640D for backside metal rails in M−1 layer may extend in the X-direction, while layout patterns 710A-710E for backside metal rails in M−2 layer may extend in the Y-direction.” ¶ [0057]), and
wherein the first backside wiring pattern is spaced apart from the second backside wiring pattern in the first direction (“layout patterns 710A-710E for backside metal rails in M−2 layer may extend in the Y-direction.” ¶ [0057]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to orient Huang’s backside power lines in the second direction and to space the supply line from the ground line along the first direction as described in Peng et al. in order to provide further flexibility in placement and routing, and allows an integrated circuit to be designed in a compact form (Peng et al. ¶ [0057]).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 and 10-14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Peng; Shih-Wei (US 20210391318 A1) “Peng et al.”.
Regarding Independent Claim 1, Peng et al. Figs. 1-2 discloses, an integrated circuit (“an integrated circuit” ¶ [0033]) comprising:
a power rail (“a backside power rail layer BM including backside power rails 210A, 210B” ¶ [0042]) extending in a first direction and configured to receive a supply voltage (“the backside power rail 210A is configured to provide a supply voltage VDD.” ¶ [0043]);
a gate line (“gate regions 220A-220C” ¶ [0045]) below the power rail and extending in a second direction that intersects the first direction;
a source/drain region (“source/drain regions 262A, 262B” ¶ [0045]) adjacent to the gate line in the first direction (“gate region 220B is formed between the source/drain regions 262A, 262B” ¶ [0045]) and configured to receive the supply voltage from the power rail;
a frontside wiring layer (“a conductive layer MD including MD regions 265A-265C can be formed according to the layout patterns 165A-165C. Above the conductive layer MD along the Z-direction, a contact layer VD including a via contact 275 can be formed according to the layout pattern 175. Above the contact layer VD along the Z-direction, a front side metal layer M0 including a front side metal rail 270 can be formed according to the layout pattern 170A.” ¶ [0042]]) above the power rail, connected to the power rail (“the MD region 265A can be used as a local interconnect rail to electrically connect nearby components (e.g., metal rails and/or source/drain/gate regions)” ¶ [0043]), and configured to transmit the supply voltage to the power rail (“the supply voltage VDD can be provided to the source region 262A and the MD region 265A through the via contact 250A, the backside metal rail 240A, and the via contact 260A.” ¶ [0043]); and
a backside wiring layer below the power rail (“The backside metal rail 240C may be implemented as a backside interconnect rail.” ¶ [0044]; “power rail layer BM including backside power rails 210A, 210B”; “a contact layer VB including via contacts 250A, 250C” ¶ [0042]), connected to the power rail (“The backside metal rail 240C may be implemented as a backside interconnect rail.” ¶ [0044]), and configured to transmit the supply voltage to the power rail (“the supply voltage VDD can be provided to the source region 262A and the MD region 265A through the via contact 250A, the backside metal rail 240A, and the via contact 260A.” ¶ [0043]).
Regarding Claim 2, Peng et al. discloses the limitations of claim 1. Peng et al. Figs. 1-2 further discloses, further comprising a backside via (“a contact layer VB including via contacts 250A, 250C” ¶ [0042]), extending in a vertical direction on the backside wiring layer (“the contact layer VB along the Z-direction, a backside metal rail layer M−1 including backside metal rails 240A-240C” ¶ [0042]),
wherein the backside wiring layer is connected (Figs. 2A-2B shows VB connects BM/250 and M-1/240) to the power rail through the backside via (“VB layer including the via contact 250A along the Z-direction, the backside metal rail 240A is formed” ¶ [0043]).
Regarding Claim 3, Peng et al. discloses the limitations of claim 2. Peng et al. Figs. 1-2 further discloses further comprising:
a contact (“metal rails 240A-240C” ¶ [0042]) extending in the vertical direction on the backside via (“a contact layer VB including via contacts 250A, 250C” ¶ [0042]); and
a contact via on the contact (“Above the backside metal rail layer M−1 along the Z-direction, a contact layer VDB including via contacts 260A-260C can be formed” ¶ [0042]),
wherein the backside wiring layer is connected to the power rail 210 through the backside via VB, the contact 240, and the contact via VDB (“the backside power rail 210A is configured to provide a supply voltage VDD. On the backside power rail 210A along the Z-direction, the via contact 250A is formed. On the VB layer including the via contact 250A along the Z-direction, the backside metal rail 240A is formed. The backside metal rail 240A may be implemented as a backside interconnect rail below (e.g., an opposite direction of the Z-direction) the source region 262A. On the backside metal rail 240A along the Z-direction, the via contact 260A is formed” ¶ [0043]).
Regarding Claim 4, Peng et al. discloses the limitations of claim 1. Peng et al. Figs. 1-2 further discloses further comprising a power rail via on the power rail (“the backside power rail 210A is configured to provide a supply voltage VDD. On the backside power rail 210A along the Z-direction, the via contact 250A is formed.” ¶ [0043]),
wherein the frontside wiring layer is connected to the power rail through the power rail via (“the MD region 265A can be used as a local interconnect rail to electrically connect nearby components (e.g., metal rails and/or source/drain/gate regions). In one aspect, a side or a surface of the source region 262A facing in the Z-direction is directly coupled to the MD region 265A, and a side or a surface of the source region 262A facing in an opposite direction of the Z-direction is directly coupled to the via contact 260A. In this configuration, the supply voltage VDD can be provided to the source region 262A and the MD region 265A through the via contact 250A, the backside metal rail 240A, and the via contact 260A.” ¶ [0043]).
Regarding Claim 5, Peng et al. discloses the limitations of claim 1. Peng et al. Figs. 1-2 further discloses wherein the frontside wiring pattern (“the front side metal rail 270 through the via contact 275” ¶ [0046]) at least partially overlaps (Fig. 2A-2B show M0/270 overlap with M1/240) the backside wiring pattern (“the backside metal rail 240B through the via contact 260B.” ¶ [0046]).
Regarding Independent Claim 10, Peng et al. Figs. 1-2 discloses, an integrated circuit comprising:
a source region (“262A” ¶ [0045]);
a drain region (“262B” ¶ [0045]) spaced apart from the source region in a first direction;
a gate line between the source region and the drain region (“the gate region 220B is formed between the source/drain regions 262A, 262B” ¶ [0045]), the gate line extending in a second direction that intersects to the first direction (Figs. 1-2 discloses, the gate line extending in a second direction that intersects to the first direction);
a frontside wiring layer (“a conductive layer MD including MD regions 265A-265C can be formed according to the layout patterns 165A-165C. Above the conductive layer MD along the Z-direction, a contact layer VD including a via contact 275 can be formed according to the layout pattern 175. Above the contact layer VD along the Z-direction, a front side metal layer M0 including a front side metal rail 270 can be formed according to the layout pattern 170A.” ¶ [0042]]) above the gate line (Figs. 2A-2B shows frontside wiring layer above the gate line 220B); and
a backside wiring layer (“The backside metal rail 240C may be implemented as a backside interconnect rail.” ¶ [0044]; “power rail layer BM including backside power rails 210A, 210B”; “a contact layer VB including via contacts 250A, 250C” ¶ [0042]) below the gate line (Figs. 2A-2B shows backside wiring layer below the gate line 220B),
wherein the frontside wiring layer comprises a first frontside wiring pattern (“the front side metal rail 270 through the via contact 275 and the MD region 265B, and is electrically coupled to the backside metal rail 240B through the via contact 260B. Hence, electrical signals can be provided through the front side metal rail 270, through the backside metal rail 240B, or both.” ¶ [0046]) extending in the first direction, connected to the source region, and configured to transmit a supply voltage to the source region (“the supply voltage VDD can be provided to the source region 262A and the MD region 265A through the via contact 250A, the backside metal rail 240A, and the via contact 260A.” ¶ [0043]; “” ¶), and
wherein the backside wiring layer comprises a first backside wiring pattern (the backside metal rail 240A, and the via contact 260A.” ¶ [0043]) connected to the source region and configured to transmit the supply voltage to the source region (“the supply voltage VDD can be provided to the source region 262A and the MD region 265A through the via contact 250A, the backside metal rail 240A, and the via contact 260A.” ¶ [0043]).
Regarding Claim 11, Peng et al. discloses the limitations of claim 10. Peng et al. Figs. 1-2 further discloses, further comprising a backside via (“a contact layer VB including via contacts 250A, 250C” ¶ [0042]), on the backside wiring layer (“the contact layer VB along the Z-direction, a backside metal rail layer M−1 including backside metal rails 240A-240C” ¶ [0042]),
wherein the backside wiring layer is connected (Figs. 2A-2B shows VB connects BM/250 and M-1/240) to the source region through the backside via (“VB layer including the via contact 250A along the Z-direction, the backside metal rail 240A is formed” ¶ [0043]).
Regarding Claim 12, Peng et al. discloses the limitations of claim 10. Peng et al. Figs. 1-2 further discloses, further comprising:
a contact on the source region (“On the source region 262A along the Z-direction, the MD region 265A is formed.” ¶ [0043]); and
a contact via on the contact (“The front side metal rails may include metal or any conductive material. The front side metal rails may be on a M0 layer. The front side metal rails may be electrically connected to the transistor (e.g., source region, drain region, or gate region) through via contacts formed according to the layout patterns 175, 180.” ¶ [0039]),
wherein the frontside wiring pattern is connected to the source region through the contact via (“The front side metal rails may include metal or any conductive material. The front side metal rails may be on a M0 layer. The front side metal rails may be electrically connected to the transistor (e.g., source region, drain region, or gate region) through via contacts formed according to the layout patterns 175, 180.” ¶ [0039]).
Regarding Claim 13, Peng et al. discloses the limitations of claim 10. Peng et al. Figs. 1-2 further discloses, wherein the frontside wiring layer further comprises a second frontside wiring pattern connected to the drain region and extending in the first direction (“the drain region 262B is electrically coupled to the front side metal rail 270 through the via contact 275 and the MD region 265B, and is electrically coupled to the backside metal rail 240B through the via contact 260B. Hence, electrical signals can be provided through the front side metal rail 270, through the backside metal rail 240B, or both.” ¶ [0046]).
Regarding Claim 14, Peng et al. discloses the limitations of claim 13. Peng et al. Figs. 1-2 further discloses, wherein the second frontside wiring pattern (“the front side metal rail 270 through the via contact 275” ¶ [0046]) at least partially overlaps (Fig. 2A-2B show M0/270 overlap with M1/240) the first backside wiring pattern (“the backside metal rail 240B through the via contact 260B.” ¶ [0046]).
Conclusion
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/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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