DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
2. Applicant’s election without traverse of Species A, identified as encompassing claims 1-3, 6-7, and 11-12 is acknowledged.
Note by the Examiner
3. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claim(s) 1-2, 6-7, and 11-12 are rejected under 35 U.S.C. 102(a1)&(a2) as being anticipated by Tang (US 2023/0018639 A1), hereinafter as T1
5. Regarding Claim 1, T1 discloses a semiconductor memory device (in particular see Figs. 4A-C and [0111] “semiconductor structure”; note, similarities for elements already described in previous embodiments may not be repeated) comprising:
a substrate (element 10, see [0116] “substrate 10”; see Figs. 2A-L for the substrate shown);
a plurality of memory layers (layers of the capacitor elements 24 and transistors of the gate elements 17, see [0112]) arranged in a first direction (Z-axis direction in Fig. 4A) intersecting with a surface of the substrate (top surface of the substrate, see [0116]; see Figs. 2A-L for illustration of the substrate); and
a first via wiring (first element 22, see [0112]) extending in the first direction, wherein the plurality of memory layers each comprises:
a first semiconductor layer (first element 131,132,25, see [0115]; also see [0091] “The exposed second semiconductor layers 112 respectively form first active pillars 131 and second active pillars 132”) electrically connected to the first via wiring (see [0117] “A bit line structure 22 is formed on each second active pillar 132” and Fig. 4C);
a first gate electrode (first element 171, see [0115] “gate structure 171”) facing surfaces on one side and the other side in the first direction, of the first semiconductor layer (see Fig. 4C);
a memory portion (element 24, see [0117] “capacitor structure 24”) which is provided on one side in a second direction (Y direction) intersecting with the first direction with respect to the first semiconductor layer (see Fig. 4A-C), and is electrically connected to the first semiconductor layer (see Fig. 4A-C and [0117]); and
a first wiring (first element 172, see [0119]) which is provided on the other side in the second direction with respect to the first semiconductor layer (see Fig. 4A), is electrically connected to the first gate electrode (see Fig. 4A), and extends in a third direction (X direction) intersecting with the first direction and the second direction (see Fig. 4A).
6. Regarding Claim 2, T1 discloses the semiconductor memory of claim 1, wherein
the first gate electrode faces surfaces on one side and the other side in the third direction (see in particular Fig. 4C), of the first semiconductor layer.
7. Regarding Claim 6, T1 discloses the semiconductor memory of claim 1, wherein the memory portion comprises:
a first electrode (see Fig. 4B element 243, see [0113]) electrically connected to the first semiconductor layer (see Fig. 4C);
a second electrode (comprising element 241, see [0113]) facing the first electrode (see Fig. 4B); and
a first insulating layer (element 242, see [0113]) provided between the first electrode and the second electrode (see Fig. 4B).
8. Regarding Claim 7, T1 discloses the semiconductor memory of claim 6, wherein
the memory portion comprises:
a first conductive layer (element 241) which is included in the second electrode;
a second conductive layer (element 242) which is included in the first electrode, and faces side surfaces on one side and the other side in the first direction of the first conductive layer (see Fig. 4B), and side surfaces on one side and the other side in the third direction of the first conductive layer (see Fig. 4B); and
a third conductive layer (element 1312, see [0091] “Each first active pillar 131 includes a first sub-pillar 1311 and a second sub-pillar 1312 … the second sub-pillar 1312 is configured to form a capacitor structure” and see Fig. 4B) which is included in the second electrode (the second electrode to further comprise element 1312), and faces side surfaces on one side and the other side in the first direction of the second conductive layer (see Fig. 4B), and side surfaces on one side and the other side in the third direction of the second conductive layer (see Fig. 4B).
9. Regarding Claim 11, T1 discloses the semiconductor memory of claim 1, wherein
the memory portion is a capacitor (see [0112]).
10. Regarding Claim 12, T1 discloses the semiconductor memory of claim 1, wherein
the first semiconductor layer includes: at least one element of gallium (Ga) and aluminum (Al); indium (In); zinc (Zn); and oxygen (O) (see [0049] “The second semiconductor layers 112 may be … indium aluminum arsenide, gallium aluminum arsenide, indium gallium arsenide”; and see [0091] “The exposed second semiconductor layers 112 respectively form first active pillars 131 and second active pillars 132”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
11. Claim 3 is rejected under 35 U.S.C. 103 as obvious over Tang (US 2023/0018639 A1), hereinafter as T1 in view of He et al. (US 2022/0285351 A1), hereinafter as H1
12. Regarding Claim 3, T1 discloses the semiconductor memory of claim 1, wherein
in a cross section extending in the second direction and the third direction, and including parts of the first via wiring, the first semiconductor layer, and the first gate electrode (see Figs. 4A-C).
T1 does not explicitly disclose the first semiconductor layer surrounds the first via wiring.
H1 discloses the first semiconductor layer surrounds the first via wiring (see Fig. 2 semiconductor layer element 221,225,223 surrounds the first via wiring element 203, see [0023, 0027]; also see [0016] the sense lines are equivalent to the bit lines)
The location relationship between the first via wiring and the first semiconductor layer as taught by H1 is incorporated as a location relationship between the first via wiring and the first semiconductor layer of T1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of H1 with T1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known bit line location relationship with the first semiconductor layer for another in a similar device to obtain predictable results (see H1 Figs. 3A-B).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m..
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/SAMUEL PARK/Examiner, Art Unit 2818
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