DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
2. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 14-18 are rejected under 35 U.S.C. 103 as obvious over Lin et al. (US 2022/0352180 A1), hereinafter as L1, in view of An et al. (US 6,448,114 B1), hereinafter as A1, in view of Jo et al. (US 2019/0363084 A1), hereinafter as J1
4. Regarding Claim 14, L1 discloses a semiconductor device (see Figs. 3-5C and [0036] “NS NFET 340 and the NS PFET 320”) comprising:
a first active pattern (element 209, 206B, 316 see [0038] “each of the channel layers 207 and each of the channel layers 209 include elemental Si in the form of a nanosheet”, [0037] “n-wells 316 and p-wells 314 … base fins 204B and the base fins 206B protrude from the substrate 202”, [0040] “Si substrate”) including a first lower pattern (element 206B, 316) extending in a first direction (first Y-direction in Fig. 5A) and a plurality of first sheet patterns (elements 209) spaced apart from the first lower pattern in a second direction (second Z direction in Fig. 5A);
a first gate structure (element 606, 610 portion surrounding the first stack of element 209, see [0062] “metal gate electrode (e.g., including the WFM layer 606 and the metal fill layer 610)”) disposed on the first lower pattern (see Fig. 5A), the first gate structure surrounding the plurality of first sheet patterns (see Fig. 5A);
a first source/drain pattern (see Fig. 5B first element 214N, see [0050] “S/D features 214N”) disposed on at least one side of the first gate structure (see Fig. 5B);
a second active pattern (element 207, 204B, 314 see [0038] “each of the channel layers 207 and each of the channel layers 209 include elemental Si in the form of a nanosheet”, [0037] “n-wells 316 and p-wells 314 … base fins 204B and the base fins 206B protrude from the substrate 202”, [0040] “Si substrate”) including a second lower pattern (element 204B, 314) extending in the first direction and a plurality of second sheet patterns (elements 207) spaced apart from the second lower pattern in the second direction (see Fig. 5A);
a second gate structure (element 606, 610 portion surrounding the second stack of element 207, see [0062]) disposed on the second lower pattern, the second gate structure surrounding the plurality of second sheet patterns (see Fig. 5A); and
a second source/drain pattern (see [0036] “each of the channel layers 209 are interposed between p-type S/D features 214P (as depicted in FIG. 4)”) disposed on at least one side of the second gate structure (see Fig. 4, 5B and [0036]);
L1 does not disclose a first trench defining the first lower pattern and having a first depth; a second trench defining the second lower pattern and having a second depth greater than the first depth; wherein a width of the first gate structure in the first direction is smaller than a width of the second gate structure in the first direction.
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A1 discloses (see “Labeled Fig. 1c” above) a first trench (labeled element “First Trench) defining the first lower pattern (labeled element “First Lower Pattern”, element 12 of 22a of Tile B”, see Column 3 line 33 “active layer 12”” and Column 3 lines 9-10 “active devices 22a and 22d, such as transistors”) and having a first depth (first depth of the labeled element “First Trench”); a second trench (labeled element “Second Trench”) defining the second lower pattern (labeled element “Second Lower Pattern”, element 22a of Tile C’) and having a second depth (depth of the labeled element “Second Trench”) greater than the first depth (see “Labeled Fig. 1c” above); wherein an interlayer insulating layer (see Fig. 1c, 7d element 30 and Column 3 line 38 “silicon dioxide layer 30”) is below the first lower pattern and not the second lower pattern (see “Labeled Fig. 1c” above).
The interlayer insulating layer and separation of the first and second lower patterns as taught by A1 is incorporated as an interlayer insulating layer and separation of the first and second lower patterns of L1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of A1 with L1 because the combination allows for adjustment of the first lower pattern thickness with respect to a second lower pattern thickness such as to allow use of partially depleted and floating body effects advantageous for digital circuitry (see A1 Column 2 lines 42-44); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known first and second lower pattern thickness height relationship for another to obtain predictable results (see A1 Fig. 1a-c and Column 2 lines 37-40).
L1, A1 do not appear to explicitly disclose wherein a width of the first gate structure in the first direction is smaller than a width of the second gate structure in the first direction.
J1 discloses (see in particular Figs. 1-2) wherein a width of the first gate structure (element 140a, see [0025] “first gate structure 140a”) in the first direction (first lateral direction) is smaller than a width of the second gate structure (element 140b, see [0026] “second gate structure 140b” ) in the first direction (see Fig. 1-2 and [0044] “The second gate structure 140b may have a fourth width W4 in the first direction greater than the third width W3” and [0034] “The first gate structure 140a may have a third width W3 in the first direction.”)
The width relationship between the first and second gate structures as taught by J1 is incorporated as a width relationship between the first and second gate structures of L1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of J1 with L1 because the combination allows for accommodation of two different types of transistors that have different operation voltage and speeds (see J1 [0024]); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known width relationship between the first and second gate structures for another to obtain predictable results (J1 Figs. 1-2 and [0034, 0044]).
5. Regarding Claim 15, L1, A1, J1 disclose the semiconductor device of claim 14, wherein, from an upper surface of the first gate structure, a distance to an upper surface of the first lower pattern is the same as a distance to an upper surface of the second lower pattern (see L1 [0065] “the method 100 forms the n-type S/D feature 214N and the p-type S/D features 214P (not shown) in the S/D recesses” and see Figs. 4, 12A-3B the source and drain of the n-type and p-type transistors are formed in the same process with the same shape and size).
6. Regarding Claim 16, L1, A1, J1 disclose the semiconductor device of claim 14, wherein a distance from a lowermost portion of the first lower pattern to a lower surface of the first gate structure is smaller than a distance from a lowermost portion of the second lower pattern to a lower surface of the second gate structure (see “Labeled Fig. 1c” and L1 Fig. 5A the interlayer insulating layer as combined with A1 is below the first lower pattern such that the second lower pattern has a larger distance from the lowermost portion to the lower surface of the second gate structure).
7. Regarding Claim 17, L1, A1, J1 disclose the semiconductor device of claim 14.
L1, A1, J1 as previously combined does not disclose further comprising a first insulating substrate disposed on a lower surface of the first lower pattern.
A1 further discloses (see Fig. 1c) further comprising a first insulating substrate (element 14, see Column 2 line 54 “buried oxide layer (BOX) 14”) disposed on a lower surface of the first lower pattern (see “Labeled Fig. 1c” above).
The SOI type substrate as taught by A1 is incorporated as an SOI type substrate of L1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of J1 with L1 because the combination provides significant advantages constructing transistors for digital circuitry and accommodation of floating body effect transistors for partial depletion during operation (see Column 1 lines 29-34); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known substrate type for another to obtain predictable results (L1 [0053] “the substrate 202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate”).
8. Regarding Claim 18, L1, A1, J1 disclose the semiconductor device of claim 17, wherein the first insulating substrate includes a first surface in contact with the first lower pattern and a second surface opposite to the first surface, and the first surface of the first insulating substrate includes a bottom surface of the first trench (see “Labeled Fig. 1c” above).
Allowable Subject Matter
9. Claims 1-13 and 20 are allowed.
Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reason for indicating allowable subject matter:
The prior art made of record, either singularly or in combination, does not disclose or suggest at least the claim limitations of:
10. Claim 1, “a second lower interlayer insulating layer including a third surface and a fourth surface opposite to the third surface; a second active pattern including a second lower pattern in contact with the third surface of the second lower interlayer insulating layer extending in the first direction and a plurality of second sheet patterns spaced apart from the second lower pattern in the second direction;
a second gate structure disposed on the second lower pattern, the second gate structure surrounding the plurality of second sheet patterns; and a second source/drain pattern disposed on at least one side of the second gate structure, wherein the first lower pattern has a first height from the first surface of the first substrate, and the second lower pattern has a second height, different from the first height, from the third surface of the second lower interlayer insulating layer” – as instantly claimed and in combination with the additionally claimed limitations.
All claims depending on the current claim incorporate the same allowable subject matter.
11. Claim 19, “a first rear wiring line disposed on the first insulating substrate and connected to the first source/drain pattern; and a second rear wiring line disposed on the second lower pattern and connected to the second source/drain pattern” – as instantly claimed and in combination with the additionally claimed limitations.
12. Claim 20, “a second lower interlayer insulating layer including a third surface and a fourth surface opposite to the third surface; a second active pattern including a second lower pattern being in contact with the second lower interlayer insulating layer extending in the first direction and a plurality of second sheet patterns spaced apart from the second lower pattern in the second direction; a second gate structure disposed on the second lower pattern, the second gate structure surrounding the plurality of second sheet patterns; a second source/drain pattern disposed on at least one side of the second gate structure; and a second rear wiring line disposed in the second lower interlayer insulating layer and connected to the second source/drain pattern, wherein the first lower pattern has a first height based on the first surface of the first substrate, wherein the second lower pattern has a second height greater than the first height based on the third surface of the second lower interlayer insulating layer, and wherein, from an upper surface of the first gate structure, a distance to an upper surface of the first lower pattern is the same as a distance to an upper surface of the second lower pattern” – as instantly claimed and in combination with the additionally claimed limitations.
All claims depending on the current claim incorporate the same allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure; pertinent prior art(s) and most relevant portion(s) is provided:
US 2020/0287046 (Fig. 20); US 2016/0276482 (Fig. 8); US 2007/0290271 (Fig. 1); US 2006/0008962 (Fig. 3B); US 2004/0173850 (Fig. 4); KR 100762897 B1 (see attached Fig. 3)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m..
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/SAMUEL PARK/Examiner, Art Unit 2818
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