DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
2. Applicant’s election with traverse of Species A, identified as encompassing claims 1-6 and 8-20 is acknowledged.
The arguments present that species E is directed towards a non-claimed comparative example. The Examiner notes that “comparative example” does not hold the same meaning as “prior art example” which would indicate admission of prior art and would not be claimed throughout prosecution of the current case. Furthermore, a restriction is not based solely on the initially presented claimed subject matter should the arguments mean that limitations directed towards Fig. 9 are not initially claimed – throughout the course of prosecution Applicant may amend limitations which are not part of the initially presented claims and are being restricted to a single invention. Lastly, it does not appear claim 1 is generic to all of the species, for example see Species C-E represented in Figs. 7-9 which do not have “longitudinal directions of the plurality of trench stripes disposed toward at least two directions” which show zero or one direction of the longitudinal directions of the plurality of trench stripes.
Therefore, the restriction is maintained and made final.
Note by the Examiner
3. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
4. Claims 3, 6, 9, 11-12, 14, 16, 18, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
5. Claim 3 recites “wherein the gate electrode comprises a gate pad, a gate electrode wiring directly connected to the gate pad, and a plurality of gate electrode trench stripes that are include in the plurality of trench stripes”. The current claim requires for gate electrode trench stripes to be comprised by the newly introduced gate electrode but also requires for the gate electrode trench stripes to be “include” in the plurality of trench stripes – therefore, the distinction between the elements is unclear particularly for the gate electrode trench stripes. Furthermore, the current claim depends on claim 1 which already recites the plurality of trench stripes formed of a second conductivity semiconductor which is inclusive of the polysilicon gate electrode trench stripes.
For the purposes of compact prosecution the interpretation will be taken that the plurality of trench stripes comprise a plurality of gate electrode trench stripes.
6. Claim 20 recites “a second semiconductor region having a second conductivity type is in contact with the region of plurality of trench stripes in one of the longitudinal directions, wherein a concentration of the second conductivity type of the second semiconductor region is higher than a concentration of the second conductivity type of the region of the plurality of trench stripes”.
The current claim depends on claim 1 which requires the plurality of trench stripes to have longitudinal directions of the plurality of stripes disposed toward at least two directions which correspond to Applicant’s elements T, 7, 8 which are stripe shaped trenches including polysilicon gate material element 8. There are no second semiconductor regions in contact with the trench stripes which have a higher concentration than the trench stripes; rather, it appears elements 6 are described with the language of the current claim “The plurality of body contact layers 6 are formed of the second conductivity silicon carbide having a higher impurity concentration than that of the plurality of body layers 4”. However, the element 4 does not fit the description of claim 1 for the trench stripes such that the current claim does not particularly point out and distinctly claim the Applicant’s invention.
Due to the extent of the indefinite issues of the current claim, a prior art rejection is unable to be presented. The Examiner notes, however, that prior art C1 Fig. 5 shows second semiconductor region element 62 of a second conductivity type having a higher concentration than element 7 in the same manner as the Applicant’s element 6 and 4.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 1-6 and 12-18 are rejected under 35 U.S.C. 103 as obvious over Clendennen (US 2024/0014313 A1), hereinafter as C1, in view of Ohtani (US 2022/0013664 A1), hereinafter as O1, in view of Vankatraman et al. (US 6,344,379 B1), hereinafter as V1
8. Regarding Claim 1, C1 discloses a semiconductor device (see Figs. 1-7, 14-19; the top view layout is selected as the embodiment of Fig. 14 which can be viewed 90 degrees oriented to the right such as to align with the Applicant’s perspective view) comprising:
a drain layer (element 8, see [0032] “n-type third region 8 … drain region”) formed of a first conductivity semiconductor (n-type conductivity semiconductor);
a drift layer (element 6, see [0027] “first region 6 may be referred to as a “drift region”) formed of the first conductivity semiconductor (see [0028] n-type) and on the drain layer (see Fig. 6); and
a plurality of trench stripes (see Fig. 6 and 14 elements 37 of elements 30 see [0043] “trench gate structures 30” and [0056] “upper electrode 37 may include conductive polysilicon. A gate potential is to be applied to the upper electrode 37”) having longitudinal directions (see Fig. 14 rotated 90 degrees to the right to correspond to the Applicant’s perspective view, lateral direction) and lateral directions (see Fig. 14 rotated 90 degrees to the right to correspond to the Applicant’s perspective view, vertical direction) formed of a conductive semiconductor (conductive polysilicon) and formed on the drift layer (see Fig. 6).
C1 does not disclose the conductive semiconductor is second conductivity; wherein the longitudinal directions of the plurality of trench stripes disposed toward at least two directions
O1 discloses the conductive semiconductor is second conductivity (see [0071] “gate electrodes 150 are formed by etching the polysilicon 150′ (see FIG. 5A). The polysilicon 150′ may be formed by forming polysilicon and thereafter, by injecting a p-type dopant (for example, boron) in the polysilicon by ion implantation”).
The specific conductivity type of the conductive polysilicon gate electrodes as taught by O1 is incorporated as the specific conductivity type of the conductive polysilicon gate electrodes of C1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of O1 with C1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known conductive polysilicon gate electrode material for another in a similar device to obtain predictable results (see O1 [0071]).
O1, C1 do not disclose wherein the longitudinal directions of the plurality of trench stripes disposed toward at least two directions
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V1 discloses wherein the longitudinal directions of the plurality of stripes disposed toward at least two directions (see Fig. 3 and “Labeled Fig. 3” above, each of the stripes elements 80 are wavy such that the extending direction is towards at least two directions, within the boundaries from left to right that each of the stripes take a curved path, see Column 4 lines 13-23 “a feature that is not straight or not substantially linear on its edges and includes, without limitation, features that are wavy or oscillating or that have a zig-zag or similar repetitive non-linear shape”;
Note, the three directions provided in “Labeled Fig. 3” above are illustrative examples and may be specifically selected within the extending direction boundaries).
The non-linear gate stripes as taught by V1 is incorporated as non-linear gate stripes of O1, C1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of V1 with O1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known gate stripe shape for another in a similar device for which the shapes are provided as alternatively selectable to obtain predictable results (see V1 Column 4 lines 13-23 and Figs. 3, 7-11).
9. Regarding Claim 2, C1, O1, V1 disclose the semiconductor device according to claim 1,
wherein the drain layer and the drift layer are formed of silicon carbide (see O1 [0204] “there is shown an example where the chip 2 includes silicon. However, the chip 2 may be constituted of a WBG (Wide Band Gap) semiconductor chip. The WBG semiconductor is a semiconductor which has a band gap exceeding a band gap of silicon. In this case, the chip 2 may include GaN (gallium nitride), SiC (silicon carbide)” Selected as silicon carbide).
10. Regarding Claim 3, C1, O1, V1 disclose the semiconductor device according to claim 1, further comprising:
a gate insulating film (see O1 elements 32,34-35, see [0049] “gate insulating film 32 includes a lower insulating film 34 and an upper insulating film 35”); and
a gate electrode (elements 91, 92, 81, 80, 37, see [0112] “gate pad electrode 91 and a gate finger electrode 92”, [0108] “via electrodes 80 include a plurality of gate via electrodes 81”, [0109] “connecting the plurality of gate via electrodes 81 with the upper electrode 37”),
wherein the gate electrode comprises a gate pad (element 91), a gate electrode wiring (element 92) directly connected to the gate pad, and a plurality of gate electrode trench stripes (elements 37) that are include in the plurality of trench stripes (see Fig. 6, 14),
wherein a first plurality of the plurality of gate electrode trench stripes is directly connected to the gate pad (see Fig. 14 first plurality of elements 37 of elements 30 in the element 9(9A)(9B) regions directly adjacent connected to element 91) and a second plurality of the plurality of gate electrode trench stripes is directly connected to the gate electrode wiring (see Fig. 14 second plurality of elements 37 of elements 30 in the element 9(9C)(9D) regions directly adjacent connected to element 92).
11. Regarding Claim 4, C1, O1, V1 disclose the semiconductor device according to claim 1,
wherein the longitudinal directions of the plurality of trench stripes are disposed toward three directions (see “Labeled Fig. 3” above).
12. Regarding Claim 5, C1, O1, V1 disclose the semiconductor device according to claim 3,
wherein the longitudinal directions of the plurality of gate electrode trench stripes disposed toward three directions (see “Labeled Fig. 3” above).
13. Regarding Claim 6, C1, O1, V1 disclose the semiconductor device according to claim 3,
wherein the semiconductor device is square in a top view and the gate pad is disposed in a central region of any one side of the semiconductor device (see C1 Fig. Fig. 14 the gate pad element 91 in a central region of one side).
14. Regarding Claim 12, C1, O1, V1 disclose the semiconductor device according to claim 3,
wherein the gate electrode wiring is arranged so as to surround the gate pad and the plurality of gate electrode trench stripes (see C1 Fig. 1, 14; note the manner in which the claim is currently recited does not require the gate electrode wiring to surround all four sides).
15. Regarding Claim 13, C1, O1, V1 disclose the semiconductor device according to claim 4,
wherein the three longitudinal directions, are positioned between -5 degrees to 5 degrees, between 55 degrees to 65 degrees, or between 115 degrees to 125 degrees against an orientation flat of a wafer before being segmented (see “Labeled Fig. 3” above, each of the extending directions can be selected at least to be between -5 degrees to 5 degrees because there is are turns in direction with respect to an orientation flat of a wafer which can be a side surface which can be a top or bottom side surface as viewed from the top view perspective, signaling the angle goes from positive to negative and repeated for the total number of curves; also see V1 Column 4 lines 13-23 “a feature that is not straight or not substantially linear on its edges and includes, without limitation, features that are wavy or oscillating or that have a zig-zag or similar repetitive non-linear shape";
note, the limitation “before being segmented” is directed towards a product-by-process which is not deemed to result in a materially different structure than the prior art disclosed structure).
16. Regarding Claim 14, C1, O1, V1 disclose the semiconductor device according to claim 5,
wherein the three longitudinal directions, are positioned between -5 degrees to 5 degrees, between 55 degrees to 65 degrees, or between 115 degrees to 125 degrees against an orientation flat of a wafer before being segmented (see “Labeled Fig. 3” above, each of the extending directions can be selected at least to be between -5 degrees to 5 degrees because there is are turns in direction with respect to an orientation flat of a wafer which can be a top or bottom side surface as viewed from the top view perspective, signaling the angle goes from positive to negative and repeated for the total number of curves; also see V1 Column 4 lines 13-23 “a feature that is not straight or not substantially linear on its edges and includes, without limitation, features that are wavy or oscillating or that have a zig-zag or similar repetitive non-linear shape";
note, the limitation “before being segmented” is directed towards a product-by-process which is not deemed to result in a materially different structure than the prior art disclosed structure).
17. Regarding Claim 15, C1, O1, V1 disclose the semiconductor device according to claim 4,
wherein the three longitudinal directions, are positioned between 25 degrees to 35 degrees, between 85 degrees to 95 degrees, or between 145 degrees to 155 degrees against an orientation flat of a wafer before being segmented (see “Labeled Fig. 3” above, each of the extending directions can be selected at least to be a certain angle with respect to an orientation flat of a wafer which can be a right or left side surface forming approximately a 90 degree angle with variation based on the curved paths as viewed from the top view perspective, signaling the angle goes from positive to negative and repeated for the total number of curves; also see V1 Column 4 lines 13-23 “a feature that is not straight or not substantially linear on its edges and includes, without limitation, features that are wavy or oscillating or that have a zig-zag or similar repetitive non-linear shape";
note, the limitation “before being segmented” is directed towards a product-by-process which is not deemed to result in a materially different structure than the prior art disclosed structure).
18. Regarding Claim 16, C1, O1, V1 disclose the semiconductor device according to claim 5,
wherein the three longitudinal directions, are positioned between 25 degrees to 35 degrees, between 85 degrees to 95 degrees, or between 145 degrees to 155 degrees against an orientation flat of a wafer before being segmented (see “Labeled Fig. 3” above, each of the extending directions can be selected at least to be a certain angle with respect to an orientation flat of a wafer which can be a right or left side surface forming approximately a 90 degree angle with variation based on the curved paths as viewed from the top view perspective, signaling the angle goes from positive to negative and repeated for the total number of curves; also see V1 Column 4 lines 13-23 “a feature that is not straight or not substantially linear on its edges and includes, without limitation, features that are wavy or oscillating or that have a zig-zag or similar repetitive non-linear shape";
note, the limitation “before being segmented” is directed towards a product-by-process which is not deemed to result in a materially different structure than the prior art disclosed structure)
19. Regarding Claim 17, C1, O1, V1 disclose the semiconductor device according to claim 4,
wherein the sum of the lengths of the plurality of trench stripes or the plurality of gate electrode trench stripes in each of the three directions is equal (see V1 Fig. 3 each of the three trench stripe total lengths are the same).
20. Regarding Claim 18, C1, O1, V1 disclose the semiconductor device according to claim 5,
wherein the sum of the lengths of the plurality of trench stripes or the plurality of gate electrode trench stripes in each of the three directions is equal (see V1 Fig. 3 each of the three trench stripe total lengths are the same).
21. Claim 19 is rejected under 35 U.S.C. 103 as obvious over Clendennen (US 2024/0014313 A1), hereinafter as C1, in view of Ohtani (US 2022/0013664 A1), hereinafter as O1, in view of Vankatraman et al. (US 6,344,379 B1), hereinafter as V1, in view of Sakamoto et al. (US 2001/0005031 A1), hereinafter as S1
22. Regarding Claim 19, C1, O1, V1 disclose the semiconductor device according to claim 1.
C1, O1, V1 do not disclose wherein a junction barrier Schottky diode region is implemented as an electrode formed so as to cover at least a region of the plurality of trench stripes.
S1 discloses wherein a junction barrier Schottky diode region is implemented as an electrode formed so as to cover at least a region of the plurality of trench stripes (see Fig. 38 and [0153] “Schottky diode … terminal 101 is interpreted as the anode terminal and the terminal 102 is translated as the cathode terminal, in which a Schottky junction with the electrode for the anode terminal is defined, and the p-type region 4 operating as the voltage holding area is defined within 5 im range from the Schottky junction and the n-type diffusion layer 19. The components 13d and 18e are aluminum electrodes for the gate terminal and the source terminal, respectively.”; also see Fig. 1 for a top view perspective).
The junction barrier Schottky diode region as taught by S1 is incorporated as junction barrier Schottky diode region of C1, O1, V1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of S1 with C1 because the combination can provide a Schottky diode voltage holding area with reduced overall device loss (see S1 [0153]); furthermore, the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known semiconductor device terminal implementation for another in a similar device to obtain predictable results (see S1 [0153] “This embodiment is an example suitable especially for Schottky diode.” [0154] “in the similar manner to the embodiments for the case of power MOS FET shown by FIGS. 22, 23 and 24 in which the floating p-type region 4 as the voltage holding area, a higher withstanding-voltage, low loss, low cost and low capacitance for the semiconductor device can be also established in this embodiment”).
Allowable Subject Matter
16. Claims 8-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reason for indicating allowable subject matter:
The prior art made of record, either singularly or in combination, does not disclose or suggest at least the claim limitations of:
17. Claim 8, “wherein the three longitudinal directions, are respectively arranged substantially parallel to a (11-20) plane, a (1-210) plane and a (-2110) plane of hexagonal crystal of the 4H silicon carbide” – as instantly claimed and in combination with the additionally claimed limitations.
18. Claim 9, “wherein the three longitudinal directions, are respectively arranged substantially parallel to a (11-20) plane, a (1-210) plane and a (-2110) plane of hexagonal crystal of the 4H silicon carbide” – as instantly claimed and in combination with the additionally claimed limitations.
18. Claim 10, “wherein the three longitudinal directions, are respectively arranged substantially parallel to (1- 100) plane, a (10-10) plane and a (0-110) plane of hexagonal crystal of the 4H silicon carbide” – as instantly claimed and in combination with the additionally claimed limitations.
18. Claim 11, “wherein the three longitudinal directions, are respectively arranged substantially parallel to a (1-100) plane, a (10-10) plane and a (0-110) plane of hexagonal crystal of the 4H silicon carbide” – as instantly claimed and in combination with the additionally claimed limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m..
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/SAMUEL PARK/Examiner, Art Unit 2818
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