Prosecution Insights
Last updated: April 19, 2026
Application No. 18/423,157

TECHNIQUES FOR TAGGING DATA BASED ON CHUNK SIZE

Non-Final OA §103
Filed
Jan 25, 2024
Examiner
FARROKH, HASHEM
Art Unit
2138
Tech Center
2100 — Computer Architecture & Software
Assignee
Micron Technology, Inc.
OA Round
3 (Non-Final)
89%
Grant Probability
Favorable
3-4
OA Rounds
2y 5m
To Grant
91%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allow Rate
813 granted / 912 resolved
+34.1% vs TC avg
Minimal +2% lift
Without
With
+2.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
13 currently pending
Career history
925
Total Applications
across all art units

Statute-Specific Performance

§101
6.4%
-33.6% vs TC avg
§103
42.3%
+2.3% vs TC avg
§102
17.1%
-22.9% vs TC avg
§112
19.1%
-20.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 912 resolved cases

Office Action

§103
DETAIL ACTION Notice of Pre-AIA or AIA Status 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . 2. This office action is in response to the communication mailed 03/12/2026. There are 20 claims pending in the application, Claims 1-3, 5, 16-18, and 20 have been amended. No claims have added or canceled. Continued Examination Under 37 CFR 1.114 3. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/122026 has been entered. INFORMATION CONCERNING CLAIMS: Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-4, 7-12 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Heyrman et al. “Heyrman” (US 20220365685 A1) in view of Ravimohan et al. “Ravimohan” (US 20180293014 A1) and IGAHARA et al. “Igahara” (US 2022/0261174 A1) . 4. Regarding claim 1, Heyrman teaches or discloses: “An apparatus (e.g., Fig. 1), comprising: a memory device comprising memory cells;” (e.g., Fig. 1, DRAM, SCM, ¶ 0003, DRAM is a type of random-access semiconductor memory that stores each bit of data in a memory cell). “and one or more controllers (e.g., Fig. 3, ¶ 0034, memory controller 110) coupled with the memory device (e.g., Fig. 3, DRAM, SCM) and configured to cause the apparatus to: receive a command to write data to the memory device,” (e.g., Fig. 4, ¶ 0036, In step 410, hot/cold write logic 320 receives a write command for data). “the command comprising a first indication of a first type of the data;” (e.g., Fig. 4, ¶ 0038, the write command indicating whether the data should be treated as hot data or cold data). However, Heyrman does not appear to expressly teach while: Ravimohan discloses: “determine whether a size of the data satisfies a data size threshold based at least in part on reception of the command;” (e.g., ¶ 0143) determine whether the size of data is below or above a threshold data size). “generate a second indication of a second type of the data based at least in part on the determination, wherein the second type of the data corresponds to one of hot data or cold data based at least in part on whether the size of the data satisfies the data size threshold;” (e.g., ¶ 0143, random data being below a threshold data size and sequential data being above a threshold data size. Additionally, for some example configurations, the size of the data be used to identify the data as hot or cold. For example, random data may be identified as hot data and sequential data may be labeled as cold data. Data types other than hot/cold). IGAHARA discloses: “and write the data to a buffer comprising a first plurality of blocks for storing the data in a first type of memory cells based at least in part on the second indication of the second type of the data.” “write the data to a buffer comprising a first plurality of blocks for storing the data in a first type of memory cells based at least in part on the second indication of the second type of the data.” (e.g., Fig. 1, ¶ 0182, As a result of the flush process, the data accumulated in the buffer memory 240 are forcibly written into the non-volatile memory 100; Fig. 13, ¶ 0166, When it is determined that the write data is the cold data (S33: YES), the processor 230 sets the write mode to the SLC or MLC mode, and writes new data into the non-volatile memory 100 in the SLC or MLC mode (S34); ¶ 0032, Each memory cell is able to store 1-bit or multi-bit data. Hereinafter, the number of bits that may be stored in each memory cell will be referred to as a multi-value degree … The SLC is able to store 1-bit data per memory cell. As described later, the non-volatile memory 100 includes multiple blocks BLK. For example, for each block BLK, data is written in any write mode among the PLC, QLC, TLC, MLC, SLC modes) when there is cold indication (second type indication), store data in SLC or first type of memory. Disclosures by Heyrman, Ravimohan, and Igahara are analogous because they are in the same field of endeavor and/or solving a similar or common problem. It would have been obvious to a person of having ordinary skill in the art before the effective filing date of the claimed invention to modify the modify the Hybrid Memory Mirroring Using Storage Class Memory taught by Heyrman to include determining whether data corresponding to data type (e.g., hot or cold data) satisfies a threshold data size condition) disclosed by Ravimohan; furthermore, to include storing data having cold (e.g., second type) indication to Single Level Cell (SLC) memory. The motivation for determining whether data size corresponding to data type(e.g., hot data or cold data) satisfies a threshold data size condition as taught by paragraph [0033] of Ravimohan is to store hot data (e.g., random data with data size below data size threshold) in the higher speed storage device; furthermore, the motivation for storing data in the SLC as taught by Igahara because the reliability of data written in a block SLC BLK is high (e.g., see par. [0123] of Igahara). Therefore, it would have been obvious to combine teachings of Igahara and Ravimohan with Heyrman to obtain the invention as specified in the claim. 5. Regarding claim 16, Heyrman teaches or discloses: A non-transitory computer-readable medium storing code comprising instructions which, when executed by a processor of an electronic device (e.g., ¶ 0078), cause the electronic device to: receive a command to write data to a memory device, the command comprising a first indication of a first type of the data;” (e.g., Fig. 4, ¶ 0036, In step 410, hot/cold write logic 320 receives a write command for data). However, Heyrman does not appear to expressly teach while: Ravimohan discloses: “determine whether a size of the data satisfies a data size threshold based at least in part on reception of the command;” (e.g., ¶ 0143) determine whether the size of data is below or above a threshold data size). “generate a second indication of a second type of the data based at least in part on the determination, wherein the second type of the data corresponds to one of hot data or cold data based at least in part on whether the size of the data satisfies the data size threshold;” (e.g., ¶ 0143, random data being below a threshold data size and sequential data being above a threshold data size. Additionally, for some example configurations, the size of the data be used to identify the data as hot or cold. For example, random data may be identified as hot data and sequential data may be labeled as cold data. Data types other than hot/cold). IGAHARA discloses: “and write the data to a buffer comprising a first plurality of blocks for storing the data in a first type of memory cells based at least in part on the second indication of the second type of the data.” (e.g., Fig. 1, ¶ 0182, As a result of the flush process, the data accumulated in the buffer memory 240 are forcibly written into the non-volatile memory 100; Fig. 13, ¶ 0166, When it is determined that the write data is the cold data (S33: YES), the processor 230 sets the write mode to the SLC or MLC mode, and writes new data into the non-volatile memory 100 in the SLC or MLC mode (S34); ¶ 0032, Each memory cell is able to store 1-bit or multi-bit data. Hereinafter, the number of bits that may be stored in each memory cell will be referred to as a multi-value degree … The SLC is able to store 1-bit data per memory cell. As described later, the non-volatile memory 100 includes multiple blocks BLK. For example, for each block BLK, data is written in any write mode among the PLC, QLC, TLC, MLC, SLC modes) when there is cold indication (second type indication), store data in SLC or first type of memory. The motivation for combining is based on the same rational presented for rejection of claim 1. 6. Regarding claim 20, Heyrman teaches or discloses: “A method (e.g., Fig. 4), comprising: receiving a command to write data to a memory device, the command comprising a first indication of a first type of the data;” (e.g., Fig. 4, ¶ 0036, In step 410, hot/cold write logic 320 receives a write command for data). However, Heyrman does not appear to expressly teach while: Ravimohan discloses: “determining whether a size of the data satisfies a data size threshold based at least in part on reception of the command;” (e.g., ¶ 0143) determine whether the size of data is below or above a threshold data size). “generating a second indication of a second type of the data based at least in part on the determination, wherein the second type of the data corresponds to one of hot data or cold data based at least in part on whether the size of the data satisfies the data size threshold;” (e.g., ¶ 0143, random data being below a threshold data size and sequential data being above a threshold data size. Additionally, for some example configurations, the size of the data be used to identify the data as hot or cold. For example, random data may be identified as hot data and sequential data may be labeled as cold data. Data types other than hot/cold). IGAHARA discloses: “and writing the data to a buffer comprising a first plurality of blocks for storing the data in a first type of memory cells based at least in part on the second indication of the second type of the data.” (e.g., Fig. 1, ¶ 0182, As a result of the flush process, the data accumulated in the buffer memory 240 are forcibly written into the non-volatile memory 100; Fig. 13, ¶ 0166, When it is determined that the write data is the cold data (S33: YES), the processor 230 sets the write mode to the SLC or MLC mode, and writes new data into the non-volatile memory 100 in the SLC or MLC mode (S34); ¶ 0032, Each memory cell is able to store 1-bit or multi-bit data. Hereinafter, the number of bits that may be stored in each memory cell will be referred to as a multi-value degree … The SLC is able to store 1-bit data per memory cell. As described later, the non-volatile memory 100 includes multiple blocks BLK. For example, for each block BLK, data is written in any write mode among the PLC, QLC, TLC, MLC, SLC modes) when there is cold indication (second type indication), store data in SLC or first type of memory. The motivation for combining is based on the same rational presented for rejection of claim 1. 7. Regarding claims 2 and 17, taking claim 2 as exemplary Revimohan further teaches: “wherein the one or more controllers are further configured to cause the apparatus to: determine whether the first type of the data corresponds to cold data based at least in part on whether the size of the data satisfies the data size threshold, wherein the second indication of the second type of the data is based at least in part on whether the first type of the data corresponds to cold data, the second type of the data comprising hot data.” (e.g., ¶ 0143, random data being below a threshold data size and sequential data being above a threshold data size. Additionally, for some example configurations, the size of the data be used to identify the data as hot or cold. For example, random data may be identified as hot data and sequential data may be labeled as cold data. Data types other than hot/cold). 8. Regarding claims 3 and 18, taking claim 3 as exemplary, Revimohan further teaches: “wherein the one or more controllers are further configured to cause the apparatus to: determine whether the first type of the data corresponds to hot data based at least in part on whether the size of the data satisfies the data size threshold, wherein (e.g., ¶ 0143, random data being below a threshold data size and sequential data being above a threshold data size. Additionally, for some example configurations, the size of the data be used to identify the data as hot or cold. For example, random data may be identified as hot data and sequential data may be labeled as cold data. Data types other than hot/cold). 9. Regarding claims 4 and 19, taking claim 4 as exemplary, Revimohan further teaches: “wherein the one or more controllers are further configured to cause the apparatus to: select the second type of the data from a set of types of data, the set of types of data comprising the first type of the data, the second type of the data, a third type of the data, a fourth type of the data, a fifth type of the data, or a sixth type of the data, or a combination thereof, wherein the second indication of the second type of the data is based at least in part on the selection of second type of the data from the set of types of data.” (e.g., ¶ 0143, random data being below a threshold data size and sequential data being above a threshold data size. Additionally, for some example configurations, the size of the data be used to identify the data as hot or cold. For example, random data may be identified as hot data and sequential data may be labeled as cold data. Data types other than hot/cold). Revimohan teaches that data types can be other than hot data type and cold data types (e.g., plurality of other data types). 10. Regarding claims 7, Igahara further teaches: “wherein: the first plurality of blocks comprises a plurality of single-level cell memory blocks, and the first type of memory cells comprises single-level memory cells.” (e.g., ¶ 0032, the non-volatile memory 100 includes multiple blocks BLK. For example, for each block BLK, data is written in any write mode among the PLC, QLC, TLC, MLC, SLC modes). 11. Regarding claims 8, Igahara further teaches: “wherein, to write the data, the one or more controllers are configured to cause the apparatus to: write the data to the plurality of single-level cell memory blocks for storing the data in the single-level memory cells.” (e.g., ¶ 0032, Each memory cell is able to store 1-bit or multi-bit data…the non-volatile memory 100 includes multiple blocks). 12. Regarding claims 9, Igahara further teaches: “wherein: the first plurality of blocks comprises a plurality of triple-level cell memory blocks, and the first type of memory cells comprises triple-level memory cells.” (e.g., ¶ 0032, the non-volatile memory 100 includes multiple blocks BLK. For example, for each block BLK, data is written in any write mode among the PLC, QLC, TLC, MLC, SLC modes). The triple-level cells or TLC. 13. Regarding claims 10, Igahara further teaches: “wherein, to write the data, the one or more controllers are configured to cause the apparatus to: write the data to the plurality of triple-level cell memory blocks for storing the data in the triple-level memory cells.” (e.g., ¶ 0032, The multiple memory cells are able to store data in a non-volatile manner). 14. Regarding claims 11, Igahara further teaches: “wherein: the first plurality of blocks comprises a plurality of quad-level cell memory blocks, and the first type of memory cells comprises quad-level memory cells.” (e.g., ¶ 0032, the non-volatile memory 100 includes multiple blocks BLK. For example, for each block BLK, data is written in any write mode among the PLC, QLC, TLC, MLC, SLC modes). The triple-level cells or TLCs. 15. Regarding claims 12, Igahara further teaches: “wherein, to write the data, the one or more controllers are configured to cause the apparatus to: write the data to the plurality of quad-level cell memory blocks for storing the data in the quad-level memory cells.” .” (e.g., ¶ 0032, the non-volatile memory 100 includes multiple blocks BLK. For example, for each block BLK, data is written in any write mode among the PLC, QLC, TLC, MLC, SLC modes). The Quad-Level Cells or QLCs. Claims 5-6 and 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Heyrman in view of Ravimohan and Igahara as applied to claim1 above, and further in view of Vanmak “Vanmak” (US 11,385,798 B1). 16. Regarding claims 5, Heyrman in view of Ravimohan and Igahara teach all limitations included in clam 1 but does not appear to expressly teach while Vanmak discloses: “wherein the one or more controllers are further configured to cause the apparatus to: determine a chunk size of the data, wherein whether the determination size of the data satisfies the data size threshold is based at least in part on the chunk size of the data.” (e.g., col. 11, line 58 to col. 12, line 13). The size threshold values may be defined as different number of LBA blocks. The data object sizes determined based on Threshold size values. Disclosures by Heyrman, Ravimohan, Igahara, and Vanmak are analogous because they are in the same field of endeavor and/or solving a similar or common problem. It would have been obvious to a person of having ordinary skill in the art before the effective filing date of the claimed invention to modify the modify the Hybrid Memory Mirroring Using Storage Class Memory taught by Heyrman to include determining whether data corresponding to data type corresponding to data type or (e.g., hot or cold data) satisfies a threshold data size condition) disclosed by Ravimohan; furthermore, to include storing data having cold (e.g., second type) indication to Single Level Cell (SLC) memory; furthermore, data size (chunk) based on number of LBAs (e.g., object data size threshold) taught by Vanmak. The motivation for determining whether data size corresponding to data type(e.g., hot data or cold data) satisfies a threshold data size condition as taught by paragraph [0033] of Ravimohan is to store hot data (e.g., random data with data size below data size threshold) in a higher speed storage device; furthermore, the motivation for storing data in the SLC as taught by Igahara because the reliability of data written in a SLC block BLK is high (e.g., see par. [0123] of Igahara); furthermore the motivation for defining threshold size values in LBAs is to classify data sizes in logical address space (e.g., see col. 11, line 46 to col. 12, line 3 of Vanmak). Therefore, it would have been obvious to combine teachings of Vanmak, Igahara, and Ravimohan with Heyrman to obtain the invention as specified in the claim. 17. Regarding claims 6, Vanmak further teaches: “wherein the first indication comprises an extension associated with the data.” (e.g., col. 14, lines 53-67, temperature labels). For example, hot data. 18. Regarding claims 13, Vanmak further teaches: “wherein the first indication, the second indication, or both, comprises a tag indicating the first type of the data, the second type of the data, or both.” (e.g., col. 16, lines 40-43, a classification state of a data object 10B that is classified with respect to two different features (e.g., data object size and “temperature”). The temperature may include at least hot data object (e.g., the first type of data) or cold data object (e.g., the second type of data) 19. Regarding claims 14, Vanmak further teaches: “wherein, to generate the second indication, the one or more controllers are configured to cause the apparatus to: modify the tag for the data from indicating the first type of the data to the second type of the data.” (e.g., col. 2, lines 54-57, The data objects may be classified iteratively, in a sense that a decision or assignment of a data object to a specific classification may be changed over time, e.g., as a result of incoming information, data or metadata, as elaborated herein). Claims 15 rejected under 35 U.S.C. 103 as being unpatentable over Heyrman in view of Ravimohan and Igahara as applied to claim1 above, and further in view of LEE “Lee” (US 2020/0159455 A1). 20. Regarding claims 15, Heyrman in view of Ravimohan, and Igahara teach all limitations included in clam 1 but does not appear to expressly teach while Lee discloses “wherein the memory device comprises a flash-friendly file system (F2FS).” (e.g., ¶ 0102, Examples of the file system which can be used in the memory system 110 may include F2FS (Flash-Friendly File System)) including the F2FS as a file system. Disclosures by Heyrman, Ravimohan, Igahara, and Lee are analogous because they are in the same field of endeavor and/or solving a similar or common problem. It would have been obvious to a person of having ordinary skill in the art before the effective filing date of the claimed invention to modify the modify the Hybrid Memory Mirroring Using Storage Class Memory taught by Heyrman to include determining whether data corresponding to data type corresponding to data type or (e.g., hot or cold data) satisfies a threshold data size condition) disclosed by Ravimohan; furthermore, to include storing data having cold (e.g., second type) indication to Single Level Cell (SLC) memory; furthermore, furthermore to include the F2FS as a file system.. The motivation for determining whether data size corresponding to data type(e.g., hot data or cold data) satisfies a threshold data size condition as taught by paragraph [0033] of Ravimohan is to store hot data (e.g., random data with data size below data size threshold) in a higher speed storage device; furthermore, the motivation for storing data in the SLC as taught by Igahara because the reliability of data written in a SLC block BLK is high (e.g., see par. [0123] of Igahara); furthermore, the motivation for including the F2FS as taught by paragraph [0102] of Lee is to provide a more efficient file system. Therefore, it would have been obvious to combine teachings of Lee, Igahara, and Ravimohan with Heyrman to obtain the invention as specified in the claim. Response to Remarks Applicant arguments have been fully considered but they are not persuasive. Vanmak teaches that data objects are classified by temperature (e.g., hot , warm, and cold) according TBR (Time Between Rewrite). Time between rewrite indicate frequency or frequently of update. For example, aTBR with a small value can be considered a hot data. However, in response to the amendment, the Examiner has rejected the independent claim 1 as being unpatentable under 35 USC 103 over Heyrman, Ravimohan , and Igahara. Heyrman teaches data type (e.g., temperature such as hot or cold) indicated by the write command. Ravimohan teaches data size corresponding data types (e.g., hot or cold) is determine based on a size threshold. Igahara used as before for storing data in different type storage based on temperature. The independent claims 16 and 20 recited similar limitations as the independent claim 1 and rejected based on the same ground of rejection. There is no specific arguments regarding the dependent claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HASHEM FARROKH whose telephone number is (571)272-4193. The examiner can normally be reached Monday through Friday from 8:30 am - 5:00 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Mr. Tim Vo can be reached on (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see htto://pair-direct.uspto.gov. For questions regarding access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786- 9199 (IN USA OR CANADA) or 571-272-1000. /HASHEM FARROKH/ Primary Examiner, Art Unit 2138
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Prosecution Timeline

Jan 25, 2024
Application Filed
May 16, 2025
Non-Final Rejection — §103
Aug 20, 2025
Response Filed
Dec 03, 2025
Final Rejection — §103
Feb 18, 2026
Response after Non-Final Action
Mar 12, 2026
Request for Continued Examination
Mar 18, 2026
Response after Non-Final Action
Mar 21, 2026
Non-Final Rejection — §103 (current)

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