DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The following information disclosure statements (IDS) submitted on
March 21, 2024
May 2, 2024
September 10, 2024
September 17, 2024
June 15, 2025
August 8, 2025
October 21, 2025
December 26, 2025
Are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 8: The claim refers to “the voltage applied to the first memory cell” but there is insufficient antecedent basis for this term.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 11 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Pasotti et al. (US 2023/0326534; hereinafter “Pasotti”).
Regarding claim 11: Pasotti (FIG. 9 and one of FIG. 10-1 or 10-2; [0095-0113]) teaches an apparatus comprising:
a memory cell array ([0095]; matrix) having sets of memory cells (rows of memory cells 14);
a controller (word line driver circuit 18 and biasing circuitry 20) configured to:
program the sets of memory cells to store a signed weight in each set ([0095]; each memory cell 14 comprises a pair of bit-cells 14mnW and 14mnS, wherein a weight value is stored in the 14W bit-cell of each memory cell and a sign of the weight value is stored in the 14S bit-cell of each memory cell) ;
apply voltages to the sets of memory cells, the voltages representing signed inputs to be multiplied by the signed weights (voltages are applied on the bit lines BLW and BLS; [0099-0104]); and
determine at least one digital result based on summing output currents from the memory cells (result Zn; [0104-0105]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3, 4, 6, 9, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pasotti et al. (US 2023/0326534; hereinafter “Pasotti”) in view of Zhang (US 2021/0232892).
Regarding claim 1: Pasotti (FIG. 9 and one of FIG. 10-1 or 10-2; [0095-0113]) teaches a device comprising:
a plurality of sets of memory cells (memory cells 14), wherein each set of memory cells is programmable to store a signed weight ([0095]; each memory cell 14 comprises a pair of bit-cells 14mnW and 14mnS, wherein a weight value is stored in the 14W bit-cell of each memory cell and a sign of the weight value is stored in the 14S bit-cell of each memory cell) for performing a multiplication ([0098, 0104]);
voltage drivers (biasing circuits 201W-mW in biasing circuitry 20) configured to apply voltages (voltages are applied on the bit lines BLW and BLS; [0099-0104]) to the sets of memory cells for performing the multiplication; and
at least one line (166 in FIG. 10-1 or 10-2) coupled to the memory cells in each set, wherein the line is configured to sum output currents from the memory cells to generate a result ([0105-0110]; a sum result Zn or the output of the ADC is generated).
Pasotti dose not specifically teach the device comprises a semiconductor substrate.
Zhang (Claims 1 and 12; FIG. 5A-B; [0054, 0057, 0059, 0060]) teaches a neuro-processing circuit comprising a multiplier on a semiconductor substrate, wherein a memory array is a 3D array.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Zhang into the device and/or method of Pasotti in a manner such that the device would comprise 3D memory array of RRAM cells like those of Pasotti on a semiconductor substrate. The motivation to do so would have been to provide a substrate to fabricate memory cells like those of Pasotti on or in. Such a substrate was common or typical in the art of semiconductor memory before the effective filing date of the invention.
Regarding claim 3: Pasotti teaches the device of claim 1, wherein the memory cells of each set are configured so that the stored weight has a value of negative one, zero, or positive one (the sign can be positive or negative; see [0095, 0099]).
Regarding claim 4: Pasotti teaches the device of claim 1, wherein the voltages are applied so that a signed input has a value of negative one, zero, or positive one (the sign can be positive or negative; see [0095, 0099]).
Regarding claim 6: Pasotti teaches the device of claim 1, wherein: each set represents a 1-bit signed weight (suffix of S is a sign bit of a corresponding weight; each sign bit is in a bit-cell 14S; [0095]); the voltages applied to each set represent a 1-bit signed input (sign bits X1s-ms; [0099]); and the result for the set (Zn) represents a signed multiplication of the 1-bit signed weight by the 1-bit signed input.
Regarding claim 9: Pasotti teaches the device of claim 1, wherein the memory cells are resistive random-access memory (RRAM) cells (see 14mn of FIG. 9; each cell has a select transistor 14t and a programmable resistor 14r), NAND flash memory cells, or NOR flash memory cells.
Regarding claim 10: Pasotti as modified above teaches the device of claim 9, wherein the RRAM cells are arranged in a memory cell array in vertical tiers extending above a semiconductor substrate (see FIG. 5a-d of Zhang), and the memory cell array further includes a respective selector in series with each RRAM cell (see 14t of FIG. 9 of Pasotti), wherein the selectors are configured for selecting RRAM cells on any one or more of the tiers, and wherein the RRAM cells are selected based on a multiplication operation to be performed (as is disclosed by Pasotti so perform a MAC operation).
Claim(s) 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pasotti et al. (US 2023/0326534; hereinafter “Pasotti”) in view of Wu et al. (US 11,953,966; hereinafter “Wu”).
Regarding claim 17: Pasotti (FIG. 9 and one of FIG. 10-1 or 10-2; [0095-0113]) teaches a method comprising:
programming sets of memory cells (rows of memory cells, wherein each memory cell has a programmed resistivity in each of two bit-cells, one that stores a weight value and another that stores a weight sign; [0095, 0100-0103]);
applying voltages (voltages are applied on the bit lines BLW and BLS; [0099-0104]) to the sets of memory cells, the voltages representing signed inputs (input bits X1V-mV having corresponding sign bits X1S-mS) to be multiplied by signed weights (weight bits stored in 14W bit-cells and their signs stored in 14S bit-cells);
summing, using at least one common line (166 in FIG. 10-1 or 10-2) coupled to the memory cells in each set, output currents from the memory cells ([0105-0110]; a sum result Zn or the output of the ADC is generated); and
generating, using at least one digitizer (ADC and DSP in FIG. 9), at least one result for the multiplication based on the summed output currents from the memory cells.
Pasotti does not specifically teach:
receiving a command from a host system to write data; and
in response to receiving the command to write the data, programming sets of memory cells.
Wu (FIG. 1; lines 14-67 of column 5 and lines 1-20 of column 6) teaches a neural network processor receiving a command from a host system to write data; and in response to receiving the command to write the data, programming sets of memory cells. Wu also teaches the computing environment or system 100 can be implemented as a system-on-chip (SOC).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Wu into the device and/or method of Pasotti in a manner such that the circuit 10 of Pasotti would be included in a compute engine like that of Wu, wherein a command from a host system to write data would be received, and in response to receiving the command to write the data, sets of memory cells 14 would be programmed. The motivation to do so would have been to use the circuit 10 of Pasotti in a neural network processor like that of Wu.
Regarding claim 18: Pasotti (FIG. 9) teaches the method of claim 17, wherein the at least one common line is at least one digit line (166 in FIG. 10-1 or 10-2 may be referred to as a digit line), the system further comprising:
bitlines (BLW and BLS in FIG. 9) coupled to the memory cells in each set; and
select transistors (14t) configured to electrically connect the bitlines of each set to the at least one digit line.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pasotti (US 2023/0326534; hereinafter “Pasotti”) as modified by Wu et al. (US 11,953,966; hereinafter “Wu”), and further in view of Saxena et al. (20220309328; hereinafter “Saxena”).
Regarding claim 19: Pasotti (FIG. 9; [0032, 0076, 0089, 0104, 120]) teaches using an analog-to-digital converter (ADC) but does not specifically teach the method of claim 17, wherein the digitizer includes at least one integrator that accumulates current on the at least one common line for each set, and the digitizer provides the result as a binary number (Zn).
Saxena ([0084]) teaches using an integrator stage within an ADC.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Saxena into the device and/or method of Pasotti as modified by Wu in a manner such that the ADC would include an integrator stage to accumulate current on the at least one common lines for each set, and the digitizer would provide the result as a binary number (Zn). The motivation to do so would have been to use an integrator stage in the ADC as exemplified by Saxena.
Allowable Subject Matter
Claims 2, 5, 7, 12-16, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY W RADKE whose telephone number is (571)270-1622. The examiner can normally be reached M-F 9-6 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JAY W. RADKE
Primary Examiner
Art Unit 2827
/JAY W. RADKE/Primary Examiner, Art Unit 2827