Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 15 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai (US 20210104525 A1).
Regarding claim 1, Tsai discloses a semiconductor device (Fig. 2) comprising:
a substrate (10) where a first region (See annotated figure) and a second region (See annotated figure) are provided;
a transistor layer (See annotated figure) spaced from the substrate (spaced in the Z direction); and
a first wiring layer (See annotated figure, this layer includes a collection of wirings including wordlines and bitlines) farther from the substrate than the transistor layer (this layer designation includes the transistor layer and extends beyond the transistor layer farther in the Z direction), wherein the transistor layer includes, in the first region:
a plurality of first oxide semiconductor layers (120; [0030]: “oxide semiconductor”) extending in a first direction (Z direction, See annotated figure for direction designation) intersecting with a surface of the substrate (the Z direction is intersecting the substrate) and being arranged in a second direction (X direction, See annotated figure for direction designation) intersecting with the first direction (the X direction is intersecting the Z direction);
a first wiring (WL1) extending in the second direction (as shown by perspective view in Fig. 1) and being opposed to the plurality of first oxide semiconductor layers (“opposed” consistent with Applicant’s disclosure, Fig. 4: wiring WL “opposed” to layers 130); and
a plurality of gate insulating films (122) provided between the plurality of first oxide semiconductor layers and the first wiring (Fig. 2 shows “between” in the Y direction, while Fig. 1 shows “between” in the X and Y directions),
the first wiring layer includes a plurality of second wirings (BL1, BL2; “plurality” is shown in Fig. 1) arranged in the second direction (arranged parallel in the X direction) and electrically connected (directly electrically connected) to respective one ends of the plurality of first oxide semiconductor layers, in the first region,
the transistor layer includes a plurality of cavities (AG) arranged in one of the second direction or a third direction (selecting “a third direction”, Y Direction, See annotated figure for direction designation) intersecting with the first direction and the second direction (the Y direction is intersecting the Z and X directions) at first pitches (pitches in the Y direction. Note: this pitch is measuring the distance of replication, consistent with the ordinary and customary meaning, and also the meaning in Applicant’s disclosure), in the second region,
the first wiring layer includes a first conductive layer (BL3, as shown in Fig. 1) in the second region, and
a plurality of recessed portions (respective “portions” of 20 at each WL1/WL2/WL3, filled by WL1/WL2/WL3. See annotated Fig. 1 for a top-down view designating the portions assigned to the first and second regions. Note: these “portions” of 20 at each 120 are “recessed portions” because Figs. 5-6 show forming the WLs includes forming a recess; Fig. 5: OP1/OP2) arranged in the one of the second direction or the third direction (“the third direction” has already been selected, and these portions are arranged in this direction) at the first pitches (Note: these recessed portions are components of a replicated structure, thus all components of the replicated structure must have the same pitch as the replication, when measured in the same direction) are provided on a surface (indirectly “on”) of the first conductive layer in the first direction on a side farther from the substrate than the other surface of the first conductive layer in the first direction (See annotated Fig. 1 for surface designations), wherein
the plurality of recessed portions are provided at positions overlapping (fully overlapping in at least the Y direction; tapered sidewalls Fig. 5: S1/S2 show at least some overlapping in the Z direction) with the plurality of cavities viewed in the first direction (Note: each situation of overlap would be visible in the Z direction because these structures are at least partially aside each other).
Illustrated below are marked and annotated figures of Figs. 1 and 2 of Tsai.
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Allowable Subject Matter
Claims 1, 4-10, and 12-14 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowable subject matter of claims 1, 4, and 7-9 is the inclusion of the limitation “wherein the surface on the side far from the substrate of the first conductive layer includes: a plurality of first parts arranged at the first pitches in the second direction or the third direction; and a plurality of second parts alternately arranged with the plurality of first parts in the second direction or the third direction, and the plurality of first parts are closer to the substrate than the plurality of second parts in the first direction” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “first parts”, “second parts”, “alternately arranged”, and “closer to the substrate” in combination with all other limitations in claim 1. Designating alternating regions of the first conductive layer as first and second parts was reasonably encompassed by the prior art, however, the claimed arrangement with respect to the substrate was not anticipated or rendered obvious by the prior art when considering all other limitations of the claim.
The primary reason for the allowable subject matter of claim 5 is the inclusion of the limitation “wherein the plurality of cavities are arranged at the first pitches in the second direction, and arranged at second pitches in the third direction, and on the surface on the side far from the substrate of the first conductive layer, the recessed portions corresponding to the first pitches are provided in the second direction, and recessed portions corresponding to the second pitches are provided in the third direction” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “first pitches”, “second pitches”, and their “direction” configuration in combination with all other limitations in claim 5. The prior art lacks any explicit teaching of the cavities being repetitious in more than one direction; and teaches a method that only reasonably suggests a single continuous cavity in a second of two directions. Additionally, “pitches” has been given the plain meaning by the examiner, consistent equally with both Applicant’s disclosure, and the ordinary and customary meanings found elsewhere in the prior art. Deriving arbitrary measurements from the prior art when also considering MPEP 2111.01 Plain Meaning, was not found capable of producing the claimed pitch and direction arrangement of the claimed structures within the scope of MPEP 2111 Broadest Reasonable Interpretation.
The primary reason for the allowable subject matter of claim 6 is the inclusion of the limitation “one end portions on a substrate side of the plurality of first oxide semiconductor layers and one end portions on the substrate side of the plurality of second oxide semiconductor layers are provided at positions approximately equal from the substrate, and lengths in the first direction of the plurality of second oxide semiconductor layers are smaller than lengths in the first direction of the plurality of first oxide semiconductor layers” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed “lengths” configuration of the “first” and “second oxide semiconductor layers”, when measured in the specific way claimed, in combination with all other limitations in claim 6.
The primary reason for the allowable subject matter of claim 10 is the inclusion of the limitation “wherein the plurality of cavities are arranged at the first pitches in the second direction, and arranged at second pitches in the third direction, and on the surface on the side far from the substrate of the first conductive layer, recessed portions corresponding to the first pitches are provided in the second direction, and recessed portions corresponding to the second pitches are provided in the third direction” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “first pitches”, “second pitches”, and their “direction” configuration in combination with all other limitations in claim 10. The prior art lacks any explicit teaching of the cavities being repetitious in more than one direction; and teaches a method that only reasonably suggests a single continuous cavity in a second of two directions. Additionally, “pitches” has been given the plain meaning by the examiner, consistent equally with both Applicant’s disclosure, and the ordinary and customary meanings found elsewhere in the prior art. Deriving arbitrary measurements from the prior art when also considering MPEP 2111.01 Plain Meaning, was not found capable of producing the claimed pitch and direction arrangement of the claimed structures within the scope of MPEP 2111 Broadest Reasonable Interpretation.
The primary reason for the allowable subject matter of claims 12-14 is the inclusion of the limitation “one end portions on the substrate side of the plurality of first oxide semiconductor layers and one end portions on the substrate side of the plurality of second oxide semiconductor layers are provided at positions approximately equal from the substrate, and lengths in the first direction of the plurality of second oxide semiconductor layers are smaller than lengths in the first direction of the plurality of first oxide semiconductor layers” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed “lengths” configuration of the “first” and “second oxide semiconductor layers”, when measured in the specific way claimed, in combination with all other limitations in claim 12.
Response to Arguments
Applicant's arguments filed 7/16/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to new claim 15 (a combination of previous claims 1 and 2, with additional limitation) that “That is, asserted recessed portions 20 are not provided in the surface of asserted first conductive layer BL3 on a side farther from the substrate than the other surface of the first conductive layer in the first direction. And, given that deficiency, Tsai does not further disclose or suggest that such recited recessed portions are provided at positions overlapping with the plurality of cavities viewed in the first direction.”. Remarks at pg. 13.
Examiner’s reply:
The examiner disagrees and points to MPEP 2111: Broadest Reasonable Interpretation. The examiner finds the claim as written reasonably encompassing configurations and surface arrangements beyond the contended features, at least because “on” as claimed reasonably includes directly “on” or indirectly “on” through intervening structures. Accordingly, claim 15 is rejected in substantially the same way as claim 2 was rejected in the non-final rejection mailed 4/21/2026. However, additional citations, annotations, and clarifying remarks have been added or adjusted as necessitated by claim amendment, and to promote clarity of the record.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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