DETAILED ACTION
This action is responsive to the response filed 27 Apr 2026 and the most recent Information Disclosure Statement filed 20 May 2026. Claims 1-20 are pending. Claims 1 and 9 are independent. Claims 19 and 20 have been restricted as independent from the originally claimed invention.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on 27 Apr 2026 has been entered.
Election/Restriction
Newly submitted claims 19 and 20 directed to an invention that is independent or distinct from the invention originally claimed for the following reasons:
Group I: Claims 1-18 drawn towards a CIM memory array with processing the input data using word lines and bit lines and then “combined”.
Group II: Claims 19-20 drawn towards a CIM memory processing of “summing currents from outputs” and “determining a sign of an accumulation”.
These two groups represent subcombinations usable together that do not overlap in scope.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 19-20 withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 1 May 2026 and 20 May 2026 are acknowledged. The submission are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Response to Arguments
Applicant’s arguments filed on 27 Apr 2026 have been fully considered. The Examiner agrees that this amendment has overcome the previous citations of the original Pasotti publication. Applicant’s arguments with respect to claims 1-18 have been considered but are moot because the arguments do not apply to the citations being used in the current rejection. In this office action, a different reference from Pasotti (U.S. Patent Application Publication 2023/0238055) have been cited to overcome the claimed inventions.
Allowable Subject Matter
Claim(s) 7 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if and only if the cited 112(b) rejections can be overcome and if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim(s) 1 - 18 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claims 1 and 9, recite the limitation, “a respective input line.”
Claims 2 and 11 recite the limitation, “the input line is a first input line”, “voltage is applied to one of the first or second input line”, and “a respective second input line” There is insufficient antecedent for “the input line” in claim 2 and for “second input line”. It is indefinite which input lines are sets or subsets of one another and if a “respective input line” is the same as “the input line”; and if the “second input line” is the same as “a respective second input line”.
Claim 1, recites the limitation “a constant voltage is applied to a respective input line”. In claim 2, “the input line IS a first input line”, then later “constant voltage is applied to ONE of the first or second input line”. It is indefinite whether or not the input line of claim 1 must still comprise a constant voltage, of if the “respective input line” of claim 1 is merely one of two different input lines with a constant voltage. then ALL of the “first input lines” must have a constant voltage
Claim 7 recites the limitation, “first memory cells in each set are configured to store a zero for each bit” and later “a position in the set of the first memory cells corresponds to a sign of the signed weight”. It is indefinite whether each first memory cells in each set must store a zero, or if the first memory cells can be configured to a second state. At least two states must exist to “correspond” to a positive state and a negative state.
Claim(s) 2-8 and 10-18 depend on rejected claim(s) 1 and 9 and are also rejected under 35 U.S.C. 112(b).
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 5, 6, 9, 10, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over PASOTTI in view of Lee, et al, U.S. Patent Application Publication 2013/0182509 (“Lee”).
Regarding claim 1, PASOTTI teaches:
(Currently Amended) A device comprising: a memory cell array having sets of memory cells, (PASOTTI , fig 1, 3, 6, “[0053] The circuit 110 utilizes a memory array 112 formed by a plurality of memory cells 14 arranged in a matrix format having n rows and m columns. [0058] It will be understood that other memory cell types could instead be used for the array 112. [0063] A column processing circuit 120 receives the analog signals on the positive and negative bit lines BL+ and BL- for the m columns and generates the multiply and accumulate (MAC) decision outputs y for the in-memory compute operation.”; a memory array comprising a set of memory cells 14, that each memory cell 14 comprises multiple signed sub-cells with multiple inputs to perform “multiply and accumulate” operations).
wherein each set is programmable to store a multi-bit signed weight; (PASOTTI , fig 1, 3, 6, “[0053] Reference is now made to FIG. 6… Each memory cell 114 includes a positive sub-cell 114pos and a negative sub-cell 114neg that are programmed to store data gmn relating to the computational weights for an in-memory compute operation. Each memory cell 114 includes a positive word line WL+, a negative word line WL-, a positive bit line BL+ and a negative bit line BL-. [0054] The word line signals 116 applied to the word lines by the word line control circuit 118 are generated from feature (or coefficient) data x input to the in-memory computation circuit 110.”; the memory array 6 which comprises a cell set 114, with sub-cells that store weights for either positive sub-cell gmn and negative sub-cell gmn weights of each based on the signs, each for the multiple bits used in the multiplication array).
voltage drivers configured to apply voltages to each set, wherein the voltages correspond to a multi-bit signed input to be multiplied by the multi-bit signed weight for each set, and (PASOTTI , fig 1, 3, 6, “[0054] The word lines WL<l>+, … , WL<n>+ and WL<l>-, … , WL<n>-are driven by a word line control circuit 118. The word line signals 116 applied to the word lines by the word line control circuit 118 are generated from feature (or coefficient) data x input to the in-memory computation circuit 110. This feature data may, for example, comprise a plurality of multi-bit digital signals Xi, … , xn that are processed by the word line control circuit 118. … In particular, each digital signal xn may include a sign bit whose logic state indicates whether the feature data is positive data or negative data.”; sets of word lines (one positive and one negative) supply lines to sets of two memory sub-cells in fig 6, similar to figs 1 and 3; in fig 6, one of two WL is activated for each memory sub-cell depending on whether the x-input data is negative (WL-) or positive (WL+)).
a (…) voltage is applied to a respective input line to represent a sign of the respective signed input; and (PASOTTI , fig 1, 2A/B, 4A/B, “[0033] The implementation illustrated in FIG. 1 shows an example in the form of a pulse width modulation (PWM) for the applied word line signals for the in-memory compute operation. [0034] FIG. 2A shows an embodiment for a digital timing control circuit 40 within the word line control circuit 18 to generate the word line signal 16 from the multi-bit digital signal x for a given word line WL. [0036] If the address enable signal is asserted (logic high) indicating that the word line is participating in the in-memory computation … and the word line signal 16 is then deasserted (logic low) to provide the trailing edge of the word line signal pulse. [0054] In the event that the sign bit is positive, then word line control circuit 118 will generate the corresponding word line signal 116 on the positive word line WL+(and the negative word line WL-is not actuated) which results in the generation of a current contribution having a charge function proportional to (+)xn x gmn on the positive bit line BL+. Conversely, if the sign bit is negative…”; that either the WL+ or WL- are activated, if one is activated with the associated pulse width, the other is deactivated; that the WL inputs are ONLY pulse width modulated, not ramped or “pulse amplitude modulated”; that the WL inputs use a timed inverter 70 of fig 2A; the timed inverter 70 represents a timed pulse which transitions from one voltage level (logic high) to another voltage level (logic low)).
at least one common line coupled to each set, wherein the common line is configured to sum output currents from the sets. (PASOTTI , fig 6, 6A/B, “[0055] A column processing circuit 120 receives the analog signals on the positive and negative bit lines BL+ and BL- for the m columns and generates the multiply and accumulate (MAC) decision outputs y for the in-memory compute operation. The column processing circuit 120 may, for example, be implemented to integrate the analog signals on each of bit lines BL+ and BL- to generate the outputs y1, … , ym, and then further process a combination of those outputs yi, … , ym to generate an overall output decision Y using a processing circuit.”; a common processing circuit 120 shown in figures 1, 3, and 6 which takes the signed multi-bit incoming data from the WL+ of WL-inputs, processes that data with the stored pos or neg weights (gmn) within the appropriate sub-cell, with the associated bit lines in the m-bit lines by n-word lines memory array to arrive at an MAC singular output, the “Decision” of fig 6, for the array).
PASOTTI does not explicitly teach a constant (voltage is applied…);.
Lee teaches a constant (voltage is applied…); (Lee, fig 1, “The method includes biasing the 1 Tl b Flash-based EEPROM cell array for reading a selected byte by applying a low read voltage level of approximately 2.5 V through the decode circuit to a selected WL associated with the selected byte, by applying a ground reference voltage level of 0 V to other unselected WLs,”; that a voltage input to a set of unselected WL can be ground, or the constant 0.0 V voltage).
In view of the teachings of Lee it would have been obvious for a person of ordinary skill in the art to apply the teachings of Lee to PASOTTI before the effective filing date of the claimed invention in order to teach reading memory cells. The teachings of Lee, in the same or in a similar field of endeavor with Pasotti, can combine Lee’s explicit “zero volt” applied to a subset of unselected WL with Pasotti’s less explicit “inactive” status for a subset of unselected WL The “zero volts” and “inactive” merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 5, PASOTTI , as modified by Lee, teaches (Original) The device of claim 1.
PASOTTI further teaches wherein summing the output currents from the sets provides a first current sum and a second current sum. (PASOTTI , fig 6, 6A/B, “[0054] In the event that the sign bit is positive, then word line control circuit 118 will generate the corresponding word line signal 116 on the positive word line WL+(and the negative word line WL-is not actuated) which results in the generation of a current contribution having a charge function proportional to (+)xnxgmn on the positive bit line BL+. [0055] A column processing circuit 120 receives the analog signals on the positive and negative bit lines BL+ and BL- for the m columns and generates the multiply and accumulate (MAC) decision outputs y for the in-memory compute operation. The column processing circuit 120 may, for example, be implemented to integrate the analog signals on each of bit lines BL+ and BL- to generate the outputs y1, … , ym, and then further process a combination of those outputs yi, … , ym to generate an overall output decision Y using a processing circuit. [0057] The positive and negative integration values y+ and y- are each converted to corresponding positive and negative digital values by the ADC circuit and combined in the digital domain by the DSP circuit to produce the y output.”; the associated sets of (+ and -) bit lines in the m x n memory array; each column comprising a total current BL+ or BL- from that column; that each of m columns provides a current to circuit 120; the BL+ currents can be summed and digitized into a first y+ value; the BL- currents can be summed and digitized into a second current sum which are then sent to a DSP to produce the y output).
Regarding claim 6, PASOTTI , as modified by Lee, teaches (Previously Presented) The device of claim 5.
PASOTTI further teaches:
further comprising a digitizer, wherein: the digitizer is further configured to (PASOTTI , fig 6, “[0055] The column processing circuit 120 may, for example, be implemented to integrate the analog signals on each of bit lines BL+ and BL- to generate the outputs y1, … , ym, and then further process a combination of those outputs yi, … , ym to generate an overall output decision Y using a processing circuit.”; the circuit 120 has a digitizer that is used to process the CIM from the memory array).
generate a first digital value based on the first current sum, and a second digital value based on the second current sum; and (PASOTTI , fig 6, 6A, “[0055] The processing circuit may include, for example, an analog-to-digital converter (ADC) circuit for each bit line BL (or pair of bit lines BL+, BL-) that functions to convert the integrated analog signal to a digital value, and a digital signal processing (DSP) circuit that functions to process the digital values output from the DACs.”; the ADC would take each successive result z1 from each time and “digitize” the result. See matrix of (i.e. 0002). Setting the g12, g13, g1m terms to zero results in a single weighted g11-x1 multiplication function for the first time slot. setting g21, g23, g2m to zero results in a single weighted g22-x2 signal in the second time slot, etc).
a sign and magnitude of a signed result are determined based on the first and second digital values. (PASOTTI , fig 6, 6A, “[0057] The operation for integration here is performed in two steps. In a first step, the column multiplexing circuit 122e selects the bit line current iBL+ on the positive bit line BL+ for integration on the capacitor C to produce a positive integration value y+. Next, in a second step, the column multiplexing circuit 122e selects the bit line current iBL- on the negative bit line BL- for integration on the capacitor C to produce a negative integration value y-. The positive and negative integration values y+ and y- are each converted to corresponding positive and negative digital values by the ADC circuit and combined in the digital domain by the DSP circuit to produce the y output.”; that the signed inputs drive the signed circuits and signed weights; that the positive or negative signals are output through the integrator circuit 220 of figures 6).
Regarding claim 9, PASOTTI teaches:
(Currently Amended) An apparatus comprising: at least one sensor; and a controller configured to: (PASOTTI , fig 1, 3, 6, “[0053] The circuit 110 utilizes a memory array 112 formed by a plurality of memory cells 14 arranged in a matrix format having n rows and m columns. [0058] It will be understood that other memory cell types could instead be used for the array 112. [0063] A column processing circuit 120 receives the analog signals on the positive and negative bit lines BL+ and BL- for the m columns and generates the multiply and accumulate (MAC) decision outputs y for the in-memory compute operation.”; a memory array comprising a set of memory cells 14, that each memory cell 14 comprises multiple signed sub-cells with multiple inputs to perform “multiply and accumulate” operations; the sensor here is a digital-to-digital input over a bus to the chip sensor rather than the argued analog-to-digital sensors).
program memory cells of each of a plurality of sets to store a respective multi-bit signed weight … receive data from the sensor; apply voltages to the sets, wherein the voltages are based on the data received from the sensor, and (PASOTTI , fig 1, 3, 6, “[0053] Reference is now made to FIG. 6… Each memory cell 114 includes a positive sub-cell 114pos and a negative sub-cell 114neg that are programmed to store data gmn relating to the computational weights for an in-memory compute operation. Each memory cell 114 includes a positive word line WL+, a negative word line WL-, a positive bit line BL+ and a negative bit line BL-. [0054] The word line signals 116 applied to the word lines by the word line control circuit 118 are generated from feature (or coefficient) data x input to the in-memory computation circuit 110.”; the memory array 6 which comprises a cell set 114, with sub-cells that store weights for either positive sub-cell gmn and negative sub-cell gmn weights of each based on the signs, each for the multiple bits used in the multiplication array).
to be multiplied by a multi-bit signed input; (PASOTTI , fig 1, 3, 6, “[0054] The word lines WL<l>+, … , WL<n>+ and WL<l>-, … , WL<n>-are driven by a word line control circuit 118. The word line signals 116 applied to the word lines by the word line control circuit 118 are generated from feature (or coefficient) data x input to the in-memory computation circuit 110. This feature data may, for example, comprise a plurality of multi-bit digital signals Xi, … , xn that are processed by the word line control circuit 118. … In particular, each digital signal xn may include a sign bit whose logic state indicates whether the feature data is positive data or negative data.”; sets of word lines (one positive and one negative) supply lines to sets of two memory sub-cells in fig 6, similar to figs 1 and 3; in fig 6, one of two WL is activated for each memory sub-cell depending on whether the x-input data is negative (WL-) or positive (WL+)).
a (…) voltage is applied to a respective input line for each set to represent a sign of the signed input; and (PASOTTI , fig 1, 2A/B, 4A/B, “[0033] The implementation illustrated in FIG. 1 shows an example in the form of a pulse width modulation (PWM) for the applied word line signals for the in-memory compute operation. [0034] FIG. 2A shows an embodiment for a digital timing control circuit 40 within the word line control circuit 18 to generate the word line signal 16 from the multi-bit digital signal x for a given word line WL. [0036] If the address enable signal is asserted (logic high) indicating that the word line is participating in the in-memory computation … and the word line signal 16 is then deasserted (logic low) to provide the trailing edge of the word line signal pulse. [0054] In the event that the sign bit is positive, then word line control circuit 118 will generate the corresponding word line signal 116 on the positive word line WL+(and the negative word line WL-is not actuated) which results in the generation of a current contribution having a charge function proportional to (+)xn x gmn on the positive bit line BL+. Conversely, if the sign bit is negative…”; that either the WL+ or WL- are activated, if one is activated with the associated pulse width, the other is deactivated; that the WL inputs are ONLY pulse width modulated, not ramped or “pulse amplitude modulated”; that the WL inputs use a timed inverter 70 of fig 2A; the timed inverter 70 represents a timed pulse which transitions from one voltage level (logic high) to another voltage level (logic low). Note: as described in the 112(a) and 112(b) rejections above, the claimed “constant voltage” is not modulated by time in the claim, so it must be continuously a “constant voltage”, or similar to V.dd which contradicts applicant’s specification. Additionally, a “constant voltage” can only represent one sign - it takes two voltage levels to represent 1 bit of information).
determine signed results based on summing output currents from the sets on at least one common line, wherein each of the signed results corresponds to a respective bit significance in the signed weights. (PASOTTI , fig 6, 6A/B, “[0055] A column processing circuit 120 receives the analog signals on the positive and negative bit lines BL+ and BL- for the m columns and generates the multiply and accumulate (MAC) decision outputs y for the in-memory compute operation. The column processing circuit 120 may, for example, be implemented to integrate the analog signals on each of bit lines BL+ and BL- to generate the outputs y1, … , ym, and then further process a combination of those outputs yi, … , ym to generate an overall output decision Y using a processing circuit.”; a common processing circuit 120 shown in figures 1, 3, and 6 which takes the signed multi-bit incoming data from the WL+ of WL-inputs, processes that data with the stored pos or neg weights (gmn) within the appropriate sub-cell, with the associated bit lines in the m-bit lines by n-word lines memory array to arrive at an MAC singular output, the “Decision” of fig 6, for the array).
PASOTTI does not explicitly teach a constant (voltage is applied…).
Lee teaches a constant (voltage is applied…) (Lee, fig 1, “The method includes biasing the 1 Tl b Flash-based EEPROM cell array for reading a selected byte by applying a low read voltage level of approximately 2.5 V through the decode circuit to a selected WL associated with the selected byte, by applying a ground reference voltage level of 0 V to other unselected WLs,”; that a voltage input to a set of unselected WL can be ground, or the constant 0.0 V voltage).
In view of the teachings of Lee it would have been obvious for a person of ordinary skill in the art to apply the teachings of Lee to PASOTTI before the effective filing date of the claimed invention in order to teach reading memory cells. The teachings of Lee, in the same or in a similar field of endeavor with Pasotti, can combine Lee’s explicit “zero volt” applied to a subset of unselected WL with Pasotti’s less explicit “inactive” status for a subset of unselected WL The “zero volts” and “inactive” merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 10, PASOTTI , as modified by Lee, teaches (Previously Presented) The apparatus of claim 9.
PASOTTI further teaches:
wherein: each signed weight comprises a first bit of a first significance, and a second bit of a second significance; (PASOTTI , fig 1, 3, 6, “[0054] The word lines WL<1>+, … , WL<n>+ and WL<2>-, … , WL<n>-are driven by a word line control circuit 118. The word line signals 116 applied to the word lines by the word line control circuit 118 are generated from feature (or coefficient) data x input to the in-memory computation circuit 110. This feature data may, for example, comprise a plurality of multi-bit digital signals Xi, … , xn that are processed by the word line control circuit 118. … In particular, each digital signal xn may include a sign bit whose logic state indicates whether the feature data is positive data or negative data.”; word lines supply lines to sets of four memory cells in fig 6, similar to figs 1 and 3; in fig 6, one of two WL is activated for each memory sub-cell depending on whether the input data is negative (WL-) or positive (WL+)).
the plurality of signed results comprises a first signed result and a second signed result; the first signed result is determined using the first bit of each signed weight; the second signed result is determined using the second bit of each signed weight; and determining an accumulation result by adding the first and second signed results. (PASOTTI , fig 6, 6A/B, “[0054] In the event that the sign bit is positive, then word line control circuit 118 will generate the corresponding word line signal 116 on the positive word line WL+(and the negative word line WL-is not actuated) which results in the generation of a current contribution having a charge function proportional to (+)xnxgmn on the positive bit line BL+. [0055] A column processing circuit 120 receives the analog signals on the positive and negative bit lines BL+ and BL- for the m columns and generates the multiply and accumulate (MAC) decision outputs y for the in-memory compute operation. The column processing circuit 120 may, for example, be implemented to integrate the analog signals on each of bit lines BL+ and BL- to generate the outputs y1, … , ym, and then further process a combination of those outputs yi, … , ym to generate an overall output decision Y using a processing circuit. [0057] The positive and negative integration values y+ and y- are each converted to corresponding positive and negative digital values by the ADC circuit and combined in the digital domain by the DSP circuit to produce the y output.”; the associated sets of (+ and -) bit lines in the m x n memory array; each column comprising a total current BL+ or BL- from that column; that each of m columns provides a current to circuit 120; the BL+ currents can be summed and digitized into a first y+ value; the BL- currents can be summed and digitized into a second current sum which are then sent to a DSP to produce the y output).
Regarding claim 16, PASOTTI , as modified by Lee, teaches (Original) The apparatus of claim 9.
PASOTTI further teaches further comprising a plurality of wordlines coupled to memory cells in each set, wherein each of the wordlines corresponds to a bit significance in the signed weights. (PASOTTI , fig 1, “[0023] The word line signals 16 applied to the word lines by the word line control circuit 18 are generated from feature (or coefficient) data x input to the in-memory computation circuit 10. This feature data may, for example, comprise a plurality of multi-bit digital signals x1, … , xn that are processed by the word line control circuit 18 to generate the word line signals 16.”; the circuit had multiple wordlines, the input data is multi-bit of x1- xn and are sent to corresponding WLs).
Regarding claim 17, PASOTTI , as modified by Lee, teaches (Original) The apparatus of claim 16.
PASOTTI further teaches wherein the at least one common line is at least one digit line, the apparatus further comprising: bitlines coupled to memory cells in each set; (PASOTTI , fig 1, 3, 6, “[0053] The circuit 110 utilizes a memory array 112 formed by a plurality of memory cells 14 arranged in a matrix format having n rows and m columns. [0058] It will be understood that other memory cell types could instead be used for the array 112. [0063] A column processing circuit 120 receives the analog signals on the positive and negative bit lines BL+ and BL- for the m columns and generates the multiply and accumulate (MAC) decision outputs y for the in-memory compute operation.”; a memory array comprising a set of memory cells 14, that each memory cell 14 comprises multiple signed sub-cells with multiple inputs to perform “multiply and accumulate” operations; that the bit lines (digit lines) are coupled to the common circuit 120 to all of the BL+ and BL- lines to perform MAC computations).
Lee teaches select transistors coupling the bitlines to the digit line; and select lines configured to control the select transistors, wherein applying the voltages comprises applying voltages on the select lines to bias gates of the select transistors. (Lee, fig 6, “But in order to prevent the leakages to the Page Buffer and stress though all 1 Tl b EEPROM cells, all top BL-select transistors 721, 722, … are biased in a nonconduction state by applying V dd on all drains nodes in each BL-select transistors along with a V dd on the common gate 725.”; that memory cell arrays typically have BL drivers comprising select transistors which apply selected voltages to the associated BLs, in this case Vdd is applied to the Select Transistors to activate each desired BL).
In view of the teachings of Lee it would have been obvious for a person of ordinary skill in the art to apply the teachings of Lee to PASOTTI before the effective filing date of the claimed invention in order to teach reading memory cells. The teachings of Lee, in the same or in a similar field of endeavor with Pasotti, can combine Lee’s explicit BL drivers with Pasotti’s less explicit BL drivers. The BL drivers merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claims 2 – 4 and 11 – 13 are rejected under 35 U.S.C. 103 as being unpatentable over PASOTTI , as modified by Lee, in view of Fujiwara, et al, U.S. Patent Application Publication 2023/0260569 (“Fujiwara”).
Regarding claim 2, PASOTTI , as modified by Lee, teaches (Currently Amended) The device of claim 1.
PASOTTI teaches wherein: the input line is a first input line; the multi-bit signed input comprises a plurality of bits; for each set, the constant voltage is applied to one of the first or second input line to represent a sign of the bits of the respective signed input; and (PASOTTI , fig 1, 3, 6, “[0054] The word lines WL<1>+, … , WL<n>+ and WL<2>-, … , WL<n>-are driven by a word line control circuit 118. The word line signals 116 applied to the word lines by the word line control circuit 118 are generated from feature (or coefficient) data x input to the in-memory computation circuit 110. This feature data may, for example, comprise a plurality of multi-bit digital signals Xi, … , xn that are processed by the word line control circuit 118. … In particular, each digital signal xn may include a sign bit whose logic state indicates whether the feature data is positive data or negative data.”; word lines supply lines to sets of four memory cells in fig 6, similar to figs 1 and 3; in fig 6, one of two WL is activated for each memory sub-cell depending on whether the input data is negative (WL-) or positive (WL+)).
PASOTTI , as modified by Lee, does not explicitly teach for each set, a varying voltage magnitude is applied to a respective second input line to represent a respective magnitude of the bits of the signed input..
Fujiwara teaches for each set, a varying voltage magnitude is applied to a respective second input line to represent a respective magnitude of the bits of the signed input. (Fujiwara, fig 1B, “[0039] For example, the analog input signals for the memory array 110 comprise various input voltage signals V1_IN, V2_IN to VN_IN supplied to the corresponding word lines WL1, WL2 to WLN. The input voltage signals V1_IN, V2_IN to VN_IN vary in one or more of amplitude, pulse duration, or the like, and correspond to the digital input data to be applied to each row of memory cells in the memory array 110”; that data can be input with variable pulse durations (taught by Pasotti) and/or with variable pulse amplitude for CIM).
In view of the teachings of Fujiwara it would have been obvious for a person of ordinary skill in the art to apply the teachings of Fujiwara to PASOTTI before the effective filing date of the claimed invention in order to teach CIM using memory cells. The teachings of Fujiwara, in the same or in a similar field of endeavor with Pasotti, can combine Fujiwara’s data input with variable amplitude and pulse duration with Pasotti’s data input with only variable pulse duration. The two similar data input methods merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 3, PASOTTI , as modified by Lee and Fujiwara, teaches (Original) The device of claim 2.
PASOTTI further teaches wherein voltages corresponding to each bit of the signed input (PASOTTI , fig 1, 3, 6, “[0032] FIG. 1 illustrates, by way of example only, the simultaneous actuation of all n word lines with the pulsed word line signals 16, it being understood that some in-memory compute operations may instead utilize a simultaneous actuation of fewer than all rows of the memory array.”; that weighted data from the WL can be input parallel for processing).
Fujiwara teaches are applied serially to the respective set. (Fujiwara, fig 1, “[0034]In one or more embodiments, the input data DA_IN, DB_IN are output data supplied from another memory macro (not shown) of the memory device l00A. In some embodiments, each of the input data DA_IN, DB_IN is serially supplied to the corresponding computation circuit 111, 112 in the form of a stream of bits.”; that weighted data for CIM can be input serially from each of the wL as DA_1N to the MAC circuit).
In view of the teachings of Fujiwara it would have been obvious for a person of ordinary skill in the art to apply the teachings of Fujiwara to PASOTTI before the effective filing date of the claimed invention in order to teach CIM using memory cells. The teachings of Fujiwara, in the same or in a similar field of endeavor with Pasotti, can combine Fujiwara’s data input with serial input with Pasotti’s parallel data input. The two similar data input methods merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 4, PASOTTI , as modified by Lee and Fujiwara, teaches (Original) The device of claim 2.
PASOTTI further teaches wherein voltages corresponding to each bit of the signed input are applied to the respective set (PASOTTI , fig 1, 3, 6, “[0032] FIG. 1 illustrates, by way of example only, the simultaneous actuation of all n word lines with the pulsed word line signals 16, it being understood that some in-memory compute operations may instead utilize a simultaneous actuation of fewer than all rows of the memory array.”; that weighted data from the WL can be input parallel for processing).
Fujiwara teaches in a series of time slices, with each time slice corresponding to one bit of the signed input. (Fujiwara, fig 1, “[0034]In one or more embodiments, the input data DA_IN, DB_IN are output data supplied from another memory macro (not shown) of the memory device l00A. In some embodiments, each of the input data DA_IN, DB_IN is serially supplied to the corresponding computation circuit 111, 112 in the form of a stream of bits.”; that weighted data for CIM can be input serially from each of the wL as DA_1N to the MAC circuit; that serially is defined as one input at a time without a time overlap).
In view of the teachings of Fujiwara it would have been obvious for a person of ordinary skill in the art to apply the teachings of Fujiwara to PASOTTI before the effective filing date of the claimed invention in order to teach CIM using memory cells. The teachings of Fujiwara, in the same or in a similar field of endeavor with Pasotti, can combine Fujiwara’s data input with serial input with Pasotti’s parallel data input. The two similar data input methods merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 11, PASOTTI , as modified by Lee, teaches (Currently Amended) The apparatus of claim 9.
PASOTTI teaches wherein: the input line is a first input line; each multi-bit signed input comprises a plurality of bits; for each set, the constant voltage is applied to one of the first or second input line to represent a sign of the bits of the respective signed input; and (PASOTTI , fig 1, 3, 6, “[0054] The word lines WL<1>+, … , WL<n>+ and WL<2>-, … , WL<n>-are driven by a word line control circuit 118. The word line signals 116 applied to the word lines by the word line control circuit 118 are generated from feature (or coefficient) data x input to the in-memory computation circuit 110. This feature data may, for example, comprise a plurality of multi-bit digital signals Xi, … , xn that are processed by the word line control circuit 118. … In particular, each digital signal xn may include a sign bit whose logic state indicates whether the feature data is positive data or negative data.”; word lines supply lines to sets of four memory cells in fig 6, similar to figs 1 and 3; in fig 6, one of two WL is activated for each memory sub-cell depending on whether the input data is negative (WL-) or positive (WL+)).
PASOTTI , as modified by Lee, does not explicitly teach for each set, a varying voltage magnitude is applied to a the other one of the first or respective second input line to represent a respective magnitude of the bits of the signed input..
Fujiwara teaches for each set, a varying voltage magnitude is applied to a the other one of the first or respective second input line to represent a respective magnitude of the bits of the signed input. (Fujiwara, fig 1B, “[0039] For example, the analog input signals for the memory array 110 comprise various input voltage signals V1_IN, V2_IN to VN_IN supplied to the corresponding word lines WL1, WL2 to WLN. The input voltage signals V1_IN, V2_IN to VN_IN vary in one or more of amplitude, pulse duration, or the like, and correspond to the digital input data to be applied to each row of memory cells in the memory array 110”; that data can be input with variable pulse durations (taught by Pasotti) and/or with variable pulse amplitude for CIM).
In view of the teachings of Fujiwara it would have been obvious for a person of ordinary skill in the art to apply the teachings of Fujiwara to PASOTTI before the effective filing date of the claimed invention in order to teach CIM using memory cells. The teachings of Fujiwara, in the same or in a similar field of endeavor with Pasotti, can combine Fujiwara’s data input with variable amplitude and pulse duration with Pasotti’s data input with only variable pulse duration. The two similar data input methods merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 12, PASOTTI , as modified by Lee and Fujiwara, teaches (Original) The apparatus of claim 11.
PASOTTI further teaches wherein voltages corresponding to each bit of the signed input are applied to the set in a series of time slices, (PASOTTI , fig 1, 3, 6, “[0032] FIG. 1 illustrates, by way of example only, the simultaneous actuation of all n word lines with the pulsed word line signals 16, it being understood that some in-memory compute operations may instead utilize a simultaneous actuation of fewer than all rows of the memory array.”; that weighted data from the WL can be input parallel for processing).
Fujiwara teaches with each time slice corresponding to one bit of the signed input. (Fujiwara, fig 1, “[0034]In one or more embodiments, the input data DA_IN, DB_IN are output data supplied from another memory macro (not shown) of the memory device l00A. In some embodiments, each of the input data DA_IN, DB_IN is serially supplied to the corresponding computation circuit 111, 112 in the form of a stream of bits.”; that weighted data for CIM can be input serially from each of the wL as DA_1N to the MAC circuit; that serially is defined as one input at a time without a time overlap).
In view of the teachings of Fujiwara it would have been obvious for a person of ordinary skill in the art to apply the teachings of Fujiwara to PASOTTI before the effective filing date of the claimed invention in order to teach CIM using memory cells. The teachings of Fujiwara, in the same or in a similar field of endeavor with Pasotti, can combine Fujiwara’s data input with serial input with Pasotti’s parallel data input. The two similar data input methods merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 13, PASOTTI , as modified by Lee and Fujiwara, teaches (Previously Presented) The apparatus of claim 12.
PASOTTI further teaches wherein at least one accumulation result comprises a first accumulation result determined at a first of the time slices, and a second accumulation result determined at a second of the time slices. (PASOTTI , fig 6, 6A/B, “[0054] In the event that the sign bit is positive, then word line control circuit 118 will generate the corresponding word line signal 116 on the positive word line WL+(and the negative word line WL-is not actuated) which results in the generation of a current contribution having a charge function proportional to (+)xnxgmn on the positive bit line BL+. [0055] A column processing circuit 120 receives the analog signals on the positive and negative bit lines BL+ and BL- for the m columns and generates the multiply and accumulate (MAC) decision outputs y for the in-memory compute operation. The column processing circuit 120 may, for example, be implemented to integrate the analog signals on each of bit lines BL+ and BL- to generate the outputs y1, … , ym, and then further process a combination of those outputs yi, … , ym to generate an overall output decision Y using a processing circuit. [0057] The positive and negative integration values y+ and y- are each converted to corresponding positive and negative digital values by the ADC circuit and combined in the digital domain by the DSP circuit to produce the y output.”; the associated sets of (+ and -) bit lines in the m x n memory array; each column comprising a total current BL+ or BL- from that column; that each of m columns provides a current to circuit 120; the BL+ currents can be summed and digitized into a first y+ value; the BL- currents can be summed and digitized into a second current sum which are then sent to a DSP to produce the y output).
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over PASOTTI , as modified by Lee, in view of PASOTTI, et al, U.S. Patent Application Publication 2023/0326499 (“PASOTTI-499”).
Regarding claim 14, PASOTTI , as modified by Lee, teaches (Original) The apparatus of claim 9.
PASOTTI , as modified by Lee, does not explicitly teach wherein a magnitude of each output current from those memory cells programmed at a state representing 1 corresponds to the respective bit significance in the signed weights..
PASOTTI-499 teaches wherein a magnitude of each output current from those memory cells programmed at a state representing 1 corresponds to the respective bit significance in the signed weights. (PASOTTI-499, fig 1, 5, “[0040] In an embodiment for a specific, but non-limiting, example for two distinct logic states: the amorphous phase may represent programming of the memory cell to logic “0” (or reset state) for the associated coefficient weight and the crystalline phase may represent programming of the memory cell to logic “1” (or set state) for the associated coefficient weight.”; that one of the inputs can be programmed to a specific value representing “null”, whether the arbitrary “1” or the arbitrary “0”; that the other part of the twin cell can be set to the opposite state, or to a linear state between the two as a weighted cell content).
In view of the teachings of PASOTTI-499 it would have been obvious for a person of ordinary skill in the art to apply the teachings of PASOTTI-499 to PASOTTI before the effective filing date of the claimed invention in order to teach CIM using memory cells. The teachings of Pasotti-499, in the same or in a similar field of endeavor with Pasotti, can combine Pasotti-499’s output with Pasotti’s less descriptive output. The two similar data output methods merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 15, PASOTTI , as modified by Lee and PASOTTI-499, teaches (Original) The apparatus of claim 14.
PASOTTI-499 further teaches wherein the magnitudes of the output currents vary by a power of two based on the bit significance corresponding to the respective output current. (PASOTTI-499, figs 4, “[0069] The current mirror circuits 221, 222 , … , 22m in FIGS. 4A-1, 4A-2, 4B-1 and 4B-2 are shown to have current mirroring ratios of A:B, A:C and A:D, respectively. In an embodiment, B, C and D may all be equal. [0070] In an alternative embodiment, however, B, C and D are not equal…. For example only, in an embodiment supporting binary weighting: B=4, C=2 and D=l.”; that each of the weights coming from the memory cells as part of the MAC function can have the same weight as they are input to the circuit 22; that the weights can all be doubled (a power of 2) by doubling the input current through a current mirror, or that the weights can be set to any binary weighting).
In view of the teachings of PASOTTI-499 it would have been obvious for a person of ordinary skill in the art to apply the teachings of PASOTTI-499 to PASOTTI before the effective filing date of the claimed invention in order to teach CIM using memory cells. The teachings of Pasotti-499, in the same or in a similar field of endeavor with Pasotti, can combine Pasotti-499’s output with Pasotti’s less descriptive output. The two similar data output methods merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over PASOTTI , as modified by Lee, in view of Khwa, et al, U.S. Patent Application Publication 2023/0317124 (“KHWA”).
PASOTTI , as modified by Lee, teaches (Original) The apparatus of claim 9.
PASOTTI teaches … each set has four memory cells; … (PASOTTI , fig 6, 6A/B, “[0054] In the event that the sign bit is positive, then word line control circuit 118 will generate the corresponding word line signal 116 on the positive word line WL+(and the negative word line WL-is not actuated) which results in the generation of a current contribution having a charge function proportional to (+)xnxgmn on the positive bit line BL+. [0055] A column processing circuit 120 receives the analog signals on the positive and negative bit lines BL+ and BL- for the m columns and generates the multiply and accumulate (MAC) decision outputs y for the in-memory compute operation. The column processing circuit 120 may, for example, be implemented to integrate the analog signals on each of bit lines BL+ and BL- to generate the outputs y1, … , ym, and then further process a combination of those outputs yi, … , ym to generate an overall output decision Y using a processing circuit. [0057] The positive and negative integration values y+ and y- are each converted to corresponding positive and negative digital values by the ADC circuit and combined in the digital domain by the DSP circuit to produce the y output.”; the associated sets of (+ and -) bit lines in the m x n memory array; each column comprising a total current BL+ or BL- from that column; that each of m columns provides a current to circuit 120; the BL+ currents can be summed and digitized into a first y+ value; the BL- currents can be summed and digitized into a second current sum which are then sent to a DSP to produce the y output).
PASOTTI , as modified by Lee, does not explicitly teach wherein: the memory cells are NAND flash memory cells; … and each memory cell of the set stores a plurality of bits representing the signed weight stored by the set..
KHWA teaches wherein: the memory cells are NAND flash memory cells; … and each memory cell of the set stores a plurality of bits representing the signed weight stored by the set. (KHWA, fig 4A, “[0020] Examples of memory elements, which are programmable to have different electrical characteristic values, include, but are not limited to, resistive random access memory (ReRAM or RRAM), magnetic RAM (MRAM), phase change memory (PCM), flash memory comprising charge storage material or floating gate, or the like. [0055] Although the memory array 40 in FIG. 4A is a NAND-type memory array, other types of memory array, such as a NOR type memory array, are also applicable. [0008] FIG. 3B illustrates a data conversion performed by a readout circuit when a read operation is performed on the MLC storing weight data of signed numbers, in accordance with some embodiments.”; that memory cells using NAND flash memory or phase change memory can be used in a standard memory array to store bits of data, MLC data, or resistive states of data as required to populate a weighted matrix for MAC operation that are summed).
In view of the teachings of KHWA it would have been obvious for a person of ordinary skill in the art to apply the teachings of KHWA to PASOTTI before the effective filing date of the claimed invention in order to teach calculations performed at the memory array. The teachings of KHWA, in the same or in a similar field of endeavor with PASOTTI, can combine KHWA’s explicit use of NAND flash memory cells and PASOTTI’s generic memory cells. The two memory types merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Conclusion
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825
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