DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-10 of U.S. Patent No. 11,908,769 (‘769) in view of U.S. Patent Application Publication 2013/0001641 to Patel et al. (Patel).
In reference to claim 1, ‘769 claims a thin-film structure (all claim 1) comprising a plurality of superlattice periods, each superlattice period comprising a first material layer disposed adjacent to a second material layer; wherein the plurality of superlattice periods comprises: a first superlattice period wherein a thickness of a first material layer of the first superlattice period is 2x and a thickness of a second material layer of the first superlattice period is 3x; a second superlattice period disposed adjacent the first superlattice period, wherein a thickness of a first material layer of the second superlattice period is 2x and a thickness of a second material layer of the second superlattice period is 4x; a third superlattice period disposed adjacent the second superlattice period, wherein a thickness of a first material layer of the third superlattice period is 2x and a thickness of a second material layer of the third superlattice period is 5x; a fourth superlattice period disposed adjacent the third superlattice period, wherein a thickness of a first material layer of the fourth superlattice period is 2x and a thickness of a second material layer of the fourth superlattice period is 6x; and a fifth superlattice period disposed adjacent the fourth superlattice period, wherein a thickness of a first material layer of the fifth superlattice period is 2x and a thickness of a second material layer of the fifth superlattice period is 7x (ALL claim 1), but does not teach wherein a thickness of each first material layer of the each superlattice period is 2x and not x.
Patel teaches a defect mitigation structures for semiconductor devices (FIG. 1-8) wherein the thickness of each first material layer (102b, FIG. 1-8) of the each superlattice period (102, FIG. 1-8) may vary from x to 4x (1000nm-4000nm, par 0032) without changing the principal desired properties, defect contentment to trap defects, for example, dislocations (par 0032) in order to improve the ductile property of the substrate while said trap defects from propagating to the top layer (par 0032).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of ‘769, to have a thickness of each first material layer of the each superlattice period is 2x and not x, as taught by Patel, in order to improve the ductile property of the substrate while said trap defects from propagating to the top layer.
In reference to claim 2, ‘769 claims and Patel teaches the thin-film structure as explained in the rejection of claim 1 above, and ‘769 additionally claims wherein, for each superlattice period, the first material layer is Bi2Te3 (claim 2).
In reference to claim 3, ‘769 claims and Patel teaches the thin-film structure as explained in the rejection of claim 1 above, and ‘769 additionally claims wherein, for each superlattice period, the second material layer is Sb2Te3 or BizTe3-xSex (claim 3).
In reference to claim 4, ‘769 claims and Patel teaches the thin-film structure as explained in the rejection of claim 1 above, and ‘769 additionally claims wherein, for each superlattice period, the first material layer and the second material layer are periodic table Group IV-VI compounds (claim 4).
In reference to claim 5, ‘769 claims and Patel teaches the thin-film structure as explained in the rejection of claim 1 above, and ‘769 additionally claims wherein, for each superlattice period, the first material layer and the second material layer are doped to be n-type semiconductor materials (claim 5).
In reference to claim 6, ‘769 claims and Patel teaches the thin-film structure as explained in the rejection of claim 1 above, and ‘769 additionally claims wherein, for each superlattice period, the first material layer and the second material layer are doped to be p-type semiconductor materials (claim 6).
In reference to claim 7, ‘769 claims and Patel teaches the thin-film structure as explained in the rejection of claim 1 above, and ‘769 additionally claims wherein the plurality of superlattice periods is a first plurality of superlattice periods; wherein the thin-film structure comprises a first band comprising the first plurality of superlattice periods and a second band comprising a second plurality of superlattice periods; wherein the first band is adjacent to the second band; and wherein the first plurality of superlattice periods of the first band and second plurality of superlattice periods of the second band have a same arrangement and thicknesses of material layers (claim 7).
In reference to claim 8, ‘769 claims and Patel teaches the thin-film structure as explained in the rejection of claim 1 above, and ‘769 additionally claims wherein the thin-film structure is a part of a thermoelectric leg comprising a bandgap gradient along the thermoelectric leg (claim 8).
In reference to claim 9, ‘769 claims and Patel teaches the thin-film structure as explained in the rejection of claim 1 above, and ‘769 additionally claims wherein the thin-film structure is a part of a thermoelectric leg comprising a doping gradient along the thermoelectric leg (claim 9).
In reference to claim 10, ‘769 claims and Patel teaches the thin-film structure as explained in the rejection of claim 1 above, and ‘769 additionally claims wherein the thin-film structure is a component of a cooler device configured to perform thermal control, thermal sensing, or energy harvesting in an electronic device, an optoelectronic device, a photonic device, a computing device, a radio frequency device, a biological platform, a micro-electro-mechanical system (MEMS), a battery system, or a sensor (claim 10).
In reference to claims 11-20, they claim the same features as claimed in claims 1-10 above; thus, said claims 11-20 are rejected in the same manner, as described in detail above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
See attached PTO-892 for relevant prior art.
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/FILIP ZEC/Primary Examiner, Art Unit 3763
11/15/2025
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