DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 20220139952).
Regarding claim 1, Kim discloses that a memory device, comprising:
a plurality of memory blocks comprising respective word lines LL1,LL2, and WL; and
a word line driver circuit comprising rows of first word line driver transistors having a source-drain direction and additional rows of second word line driver transistors having the same source-drain direction as the first word line driver transistors,
wherein: the rows of the first word line driver transistors and the additional rows of the second word line driver transistors extend along a direction that is perpendicular to the source-drain direction (Fig. 1, note: the row of the first world line driver transistor and the additional rows of the second word line driver transistors extend along a direction that is perpendicular to the source-drain direction the first word line driver transistors since additional rows of the second word line driver transistor is located between a first transistor and the second transistor of first row and offset) comprise first output nodes electrically connected to word lines in a first memory block of the plurality of memory blocks (Fig. 1);
the second word line driver transistors comprise second output nodes electrically connected to word lines in the first memory block of the plurality of memory blocks; and
the rows of the first word line driver transistors are laterally offset from the additional rows of the second word line driver transistors along the source-drain direction (Fig. 1).
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Reclaim 2, Kim discloses that the first output nodes comprise first source or drain regions of the first word line driver transistors; and the second output nodes comprise second source or drain regions of the second word line driver transistors (Fig. 1).
Reclaim 3, Kim discloses that each first source or drain region of the first word line driver transistors and each second source or drain region of the second word line driver transistors has an areal overlap with the first memory block in a plan view along a vertical direction, and does not have any areal overlap with any other memory block of the plurality of memory blocks in the plan view (Fig. 1).
Reclaim 4, Kim discloses that the plurality of memory blocks are located in a memory die; the word line driver circuit is located in a logic die; and the memory die is bonded to the logic die (Fig. 3 or 6).
Reclaim 5, Kim discloses that each of the plurality of memory blocks comprises a respective alternating stack of insulating layers and the word lines and including a respective set of rows of memory opening fill structures vertically extending through the respective alternating stack and arranged along a first horizontal direction; the memory blocks are laterally spaced apart from each other along a second horizontal direction that is perpendicular to the first horizontal direction and parallel to the source-drain direction; and wherein: the first word line driver transistors are arranged in the rows that extend along the first horizontal direction and spaced apart from each other along the second horizontal direction; the second word line driver transistors are arranged in the additional rows that extend along the first horizontal direction and spaced apart from each other along the second horizontal direction; and the rows of the first word line driver transistors and the additional rows of the second word line driver transistors are offset along the second horizontal direction by a lateral offset distance (Fig. 6).
Reclaim 6, Kim discloses that the first output nodes and the second output nodes are electrically connected to the word lines in the first memory block by interconnect structures; and all interconnect structures that provide an electrical connection between a word line in the first memory block and the first output node of a first word line driver transistor or the second output node of the second word line driver transistor are located entirely within an area of the first memory block within a plan view along a vertical direction (Fig. 1 & 6).
Reclaim 7, Kim discloses that the rows of the first word line driver transistors are arranged along the second horizontal direction with a uniform transistor row-to-row pitch; the additional rows of the second word line driver transistors are arranged along the second horizontal direction with the uniform transistor row-to-row pitch; the uniform transistor row-to-row pitch is (n+1)/n times the uniform block-to-block pitch; and n is an integer greater than 1 and less than 7 (Fig. 1 & 6).
Reclaim , Kim discloses that n is 2; the plurality of memory blocks further comprise a second memory block; and each of the first word line driver transistors and the second word line driver transistors which has an output node that is electrically connected to a word line in the first memory block comprises another output node that is electrically connected to a respective word line in the second memory block (Fig. 1 & 6).
Reclaim 9, Kim discloses that the first word line driver transistors comprise first-row first word line driver transistors and second-row first word line driver transistors that are spaced along the second horizontal direction; the second word line driver transistors comprise first-row second word line driver transistors and second-row second word line driver transistors that are spaced along the second horizontal direction; the word lines in the first memory block are electrically connected to the first output nodes of the first-row first word line driver transistors, second output nodes of the first- row second word line driver transistors, or first output nodes of the second-row second word line driver transistors; and the word lines of the second memory block are electrically connected to the second output nodes of the first-row first word line driver transistors, first output nodes of the second-row first word line driver transistors, or second output nodes of the second-row second word line driver transistors (Fig. 1 & 6).
Reclaim 10, Kim discloses that n is 3; the plurality of memory blocks further comprise a second memory block, and a third memory block; and each of the first word line driver transistors and the second word line driver transistors which has an output node that is electrically connected to the word line in the first memory block comprises another output node that is electrically connected to a respective word line in a memory block that is not the first memory block (Fig. 1 & 6)
Reclaim 11, Kim discloses that the first word line driver transistors comprise first-row first word line driver transistors and second-row first word line driver transistors that are spaced along the second horizontal direction; the second word line driver transistors comprise first-row second word line driver transistors, second-row second word line driver transistors, and third-row second word line driver transistors that are spaced along the second horizontal direction; the first output nodes of the first-row first word line driver transistors, second output nodes of the first-row second word line driver transistors, and first output nodes of the second-row second word line driver transistors are electrically connected to the respective word line in the first memory block; the second output nodes of the first-row first word line driver transistors, first output nodes of the second-row first word line driver transistors, and second output nodes of the second-row second word line driver transistors are electrically connected to a respective word line in the second memory block; and second output nodes of the second-row first word line driver transistors and first output nodes of the third-row second word line driver transistors are electrically connected to a respective word line in the third memory block (Fig. 1 & 6)
Reclaim 12, Kim discloses that the memory die further comprises rows of layer contact via structures that are arranged along the first horizontal direction; and each row of layer contact via structures contacts word lines within a respective alternating stack of the alternating stacks (Fig. 1 & 6)
Reclaim 13, Kim discloses that multiple rows of first word line driver transistors have a periodic modulation in a first row-to-row spacing along the second horizontal direction, the first row-to-row spacing being measured by a lateral spacing between a neighboring pair of first word line driver transistors that are laterally spaced along the second horizontal direction (Fig. 1 & 6)
Reclaim 14, Kim discloses that the first word line driver transistors further comprise second output nodes electrically connected to word lines in a second memory block of the plurality of memory blocks, common input nodes, a first gate electrode located between the common input node and the first output node, and a second gate electrode located between the common input node and the first output node (Fig. 1 & 6).
Allowable Subject Matter
Claims 15-20 are allowed over applicant’s argument filed on 6/25/2026.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SU C KIM whose telephone number is (571)272-5972. The examiner can normally be reached M-F 9:00 to 5:00.
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/SU C KIM/ Primary Examiner, Art Unit 2899
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