DETAILED ACTION
The Applicant Argument/Remarks filed October 17, 2025 has been entered. Claims 1-10 are pending. Claims 1 and 9 are independent.
Specification
The Amendment to the Title filed October 17, 2025 is acceptable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jaiswal et al. (US 2022/0051709).
Regarding independent claims 1 and its method claim 9, Jaiswal et al. disclose a semiconductor device which includes a plurality of memory cells, the semiconductor device (see e.g., FIG. 1) comprising:
a first memory cell (e.g., FIG. 1 and EXAMINER’S MARKUP below);
a second memory cell (e.g., FIG. 1 and EXAMINER’S MARKUP below) disposed adjacent to the first memory cell along a first direction;
a first bit line (e.g., FIG. 1 and EXAMINER’S MARKUP below) extending in a second direction perpendicular to the first direction and connected to the first memory cell;
a second bit line (e.g., FIG. 1 and EXAMINER’S MARKUP below) and a third bit line (e.g., FIG. 1 and EXAMINER’S MARKUP below) extending in the second direction between the first memory cell and the second memory cell and connected to the first memory cell and the second memory cell; and
a control unit (see FIGS. 5B-6AB) connected to the first bit line, the second bit line, and the third bit line,
wherein the control unit is configured to:
perform a read operation (see FIGS. 2B-6B and accompanying disclosure, i.e., read operation) on the first memory cell by using the first bit line; and
perform a write operation (see FIGS. 2B-6B and accompanying disclosure, i.e., write operation) on the first memory cell or the second memory cell by using the second bit line and the third bit line.
Further, regarding method claim 9, where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. Examiner has an authority to shift the burden to applicant and require applicant to either: (1) show the prior art memory device and the claimed memory device are not substantially identical; or (2) prove, by evidence, that the prior art memory device is not capable of performing the functions claimed. see MPEP 2112.01(I).
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Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-7 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Jaiswal et al. (US 2022/0051709) in view of Fan et al. (US 2024/0005976).
Regarding claim 2, Jaiswal et al. teach the limitations of claim 1.
Jaiswal et al.’ SOT MRAM does not explicitly disclose the limitations of claim 2.
Fan et al. teach the deficiencies in e.g., FIG. 3B and accompany disclosure, i.e. the first memory cell further includes: a first spin orbit torque (SOT) element (M1); a first transistor (M1 transistor connected WBL1) connected between a first end of the first SOT element and the first bit line (WBL1); and a second transistor (M1 transistor connected RBL1) connected between a second end of the first SOT element and the second bit line or the third bit line (RBL1), wherein the control unit performs the read operation on the first memory cell by applying a specified read current to the first transistor and the first SOT element through the first bit line (see FIG. 3B and accompanying disclosure, i.e., operating with read bit line and write bit line).
Jaiswal and Fan are analogous art because they both are directed to SOT MRAM device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Jaiswal with the specified features of Fan because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Fan et al. to the teaching of Jaiswal et al. such that a SOT MRAM, as taught by Jaiswal et al., utilizes a SOT MRAM structure, as taught by Fan et al., for the purpose of enabling compact memory structure, thereby enhancing read and write memory operations.
Regarding claim 3, Jaiswal et al. and Fan et al., as combined, teach the limitations of claim 2.
Jaiswal et al. and Fan et al. further teach the control unit performs the write operation on the first memory cell by applying a first voltage to the second transistor and the first SOT element through the second bit line and applying a second voltage having a preset voltage difference with the first voltage through the third bit line (see Jaiswal’s FIGS. 2B-6B and Fan’s FIG. 3B and accompanying disclosure).
Regarding claim 4, Jaiswal et al. and Fan et al., as combined, teach the limitations of claim 3.
Jaiswal et al. further teach a fourth bit line extending in the second direction and connected to the second memory cell, wherein the second memory cell includes: a second SOT element; a third transistor connected between a first end of the second SOT element and the fourth bit line; and a fourth transistor connected between a second end of the second SOT element and the second bit line and the third bit line, and wherein the control unit performs the read operation on the second memory cell by applying the read current to the third transistor and the second SOT element through the fourth bit line (e.g., FIG. 1 and accompanying disclosure).
Regarding claim 5, Jaiswal et al. and Fan et al., as combined, teach the limitations of claim 4.
Jaiswal et al. and Fan et al. further teach the control unit performs the write operation on the second memory cell by applying the first voltage to the fourth transistor and the second SOT element through the second bit line and applying the second voltage through the third bit line (see Jaiswal’s FIGS. 2B-6B and Fan’s FIG. 3B and accompanying disclosure).
Regarding claim 6, Jaiswal et al. and Fan et al., as combined, teach the limitations of claim 2.
Jaiswal et al. further teach a first word line extending in the first direction and connected to the first memory cell, and wherein the control unit is configured to: apply a word line voltage to the first word line to activate the first transistor and the second transistor of the first memory cell; and perform the read operation or the write operation on the first memory cell in response to that the first transistor and the second transistor are activated (e.g., FIG. 1 and accompanying disclosure).
Regarding claim 7, Jaiswal et al. and Fan et al., as combined, teach the limitations of claim 2.
Jaiswal et al. and Fan et al. further teach the control unit includes: a read circuit configured to generate the read current and to apply the read current to the first memory cell or the second memory cell; a write circuit configured to generate the first voltage and the second voltage and to apply the first voltage and the second voltage to the first memory cell or the second memory cell (see Jaiswal’s FIGS. 2B-6B and Fan’s FIG. 3B and accompanying disclosure).
a monitoring circuit configured to sense a voltage of the first SOT element changed by the read current applied to the first SOT element (see Jaiswal’s FIGS. 2B-6B, e.g.., para. 0030: … the sense amplifiers to sense (i.e., read) a programmed (i.e., stored) value; and Fan’s FIG. 3C, sense circuit).
.
Claim 8 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Jaiswal et al. (US 2022/0051709) in view of Fan et al. (US 2024/0005976), further in view of Pelley et al. (US 2016/0035415).
Regarding claim 8, Jaiswal et al. and Fan et al., as combined, teach the limitations of claim 3.
Jaiswal et al. and Fan et al.’ MRAM device further teach the control unit is configured to: apply a sensing current to the first SOT element through the first bit line during the write operation on the first memory cell; and when a voltage of the first SOT element changed by the sensing current satisfies a preset criterion, end the write operation performed by using the second bit line and the third bit line (see Jaiswal’s FIGS. 2B-6B and Fan’s FIG. 3B and accompanying disclosure).
Jaiswal et al. and Fan et al. do not explicitly disclose a sensing current through the bit line during the write operation.
Pelley et al. teach the deficiencies in e.g., para. 0050: … during the write operation, reading the memory cell by sensing current on a read bitline …
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Pelley et al. to the teaching of Jaiswal et al. and Fan et al. such that a SOT MRAM, as taught by Jaiswal et al. and Fan et al., as combined, utilizes a sensing during write operation, as taught by Pelley et al., for the purpose of enabling compact memory structure, thereby enhancing read and write memory operations.
Claim 10 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Jaiswal et al. (US 2022/0051709) in view of Pelley et al. (US 2016/0035415).
Regarding claim 10, Jaiswal et al. teach the limitations of claim 9.
Jaiswal et al.’ MRAM device further teach the control unit is configured to: apply a sensing current to the first SOT element through the first bit line during the write operation on the first memory cell; and when a voltage of the first SOT element changed by the sensing current satisfies a preset criterion, end the write operation performed by using the second bit line and the third bit line (see Jaiswal’s FIGS. 2B-6B).
Jaiswal et al. do not explicitly disclose a sensing current through the bit line during the write operation.
Pelley et al. teach the deficiencies in e.g., para. 0050: … during the write operation, reading the memory cell by sensing current on a read bitline …
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Pelley et al. to the teaching of Jaiswal et al. such that a SOT MRAM, as taught by Jaiswal et al., utilizes a sensing during write operation, as taught by Pelley et al., for the purpose of enabling compact memory structure, thereby enhancing read and write memory operations.
Response to Arguments
Applicant’s arguments filed 10/17/2025, with respect to the rejection(s) of claims 1-10 under 35 USC 102 and 103, have been fully considered but are not persuasive.
For a compact prosecution, the examiner points out and answers the main features of the applicant’s argument.
The applicant argus that Jaiswal is silent regarding the recited feature, “a second bit line and a third bit line connected to the first memory cell and the second memory cell”.
In response to the applicant’s argument, the examiner examines the claimed limitations.
Figure 1 of Jaiswal discloses PBL1 (claimed a second bit line) connected to the first memory cell (see EXMINER’S MARKUP above) and APBL0 (claimed a third bit line) connected to the second memory cell (see EXMINER’S MARKUP above).
The applicant argus that Jaiswal is silent regarding the recited feature, “the control unit is configure to: perform a read operation on the first memory cell by using the first bit line; and perform a write operation on the first memory cell or the second memory cell by using the second bit line and the third bit line.”
In response to the applicant’s argument, based on the explanation provided on pages 9-10 of applicant’s arguments/remarks, the applicant acknowledges that Jaiswal discloses read and write operations using first, second and third bit lines. Applicant’s claim is open-ended. Jaiswal teaches the claimed limitations of read and write operations using first, second and third bit lines.
Therefore, it is respectfully submitted that the examiner maintains the rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached on 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SUNG IL CHO/ Primary Examiner, Art Unit 2825