DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Species A1 (allegedly claims 1-20) in the reply filed on 05/19/2026 is acknowledged. The Examiner notes that claims 5-9 and 19-20 belong to unelected species and are hereby withdrawn.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/26/2024 has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: IMAGE SENSOR.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 4, 14, 15, 17, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ahn et al. (US Pub. 2014/0327051).
Regarding independent claim 1, Ahn teaches a semiconductor device including a plurality of unit pixels (Figs. 1A, 1B; para. 0035+), wherein each unit pixel of the plurality of unit pixels comprises:
a pair of transfer gates (TG_1, TG_2) including a first transfer gate (TG_1) and a second transfer gate (TG_2) (para. 0044, 0046);
a photoelectric converter (PD) (para. 0038); and
a floating diffusion region (FD) spaced apart from the photoelectric converter (para. 0045),
wherein the first transfer gate and the second transfer gate are disposed asymmetrically with respect to the photoelectric converter and the floating diffusion region (Fig. 1B).
Re claim 3, Ahn teaches wherein the first transfer gate is closer to the photoelectric converter than the floating diffusion region, and the second transfer gate is closer to the floating diffusion region than the first transfer gate (Fig. 1B).
Re claim 4, Ahn teaches wherein the second transfer gate is closer to the floating diffusion region than the photoelectric converter (Fig. 1B).
Re claim 14, Ahn teaches wherein at least part of the plurality of unit pixels further include a source follower gate (123) and a selection gate (124) (Fig. 2; para. 0048).
Re claim 15, Ahn teaches wherein at least part of the plurality of unit pixels further include a reset gate (125) (Fig. 2; para. 0048).
Regarding independent claim 17, Ahn teaches a semiconductor device (Figs. (Figs. 5A, 5B, 2, 3); para. 0035+), comprising:
a first substrate (110) having a first surface (111) and a second surface (112) opposite to the first surface, and including a pixel array region (1100) and an edge region (1200, 1300), wherein the pixel array region includes a plurality of unit pixels (Fig. 3; para. 0052+);
an anti-reflection structure (130) disposed on the second surface (Fig. 5A; para. 0037);
a pixel separator (117) disposed on the first substrate to separate the plurality of unit pixels (Figs. 5A, 5B);
a color filter (140) disposed on the anti-reflection structure (Fig. 5A; para. 0037);
a micro lens (150) array disposed on the color filter (Fig. 5A; para. 0037);
a first interlayer insulating layer (portion of 120) disposed on the first surface of the first substrate; a first wiring layer disposed within the first interlayer insulating layer; a second interlayer insulating layer (another portion of 120) disposed under the first interlayer insulating layer; a second wiring layer disposed within the second interlayer insulating layer (para. 0036 teaching a plurality of wiring layers and thus teaching at least a first wiring layer and a second wiring layer where the portions of 120 corresponding to these wiring layers are considered the first interlayer insulating layer and the second interlayer insulating layer); and
a second substrate disposed under the second interlayer insulating layer (para. 0035 – transistor layer 120 may be one of a bulk substrate, an epitaxial substrate, and an SOI substrate – that is the transistor layer 120 is formed on the “second substrate”),
wherein each unit pixel of the plurality of unit pixels comprises:
a pair of transfer gates (TG_1, TG_2) including a first transfer gate (TG_1) and a second transfer gate (TG_2) (para. 0044, 0046);
a photoelectric converter (PD) (para. 0038); and
a floating diffusion region (FD) spaced apart from the photoelectric converter (para. 0045),
wherein the first transfer gate and the second transfer gate are disposed asymmetrically with respect to the photoelectric converter and the floating diffusion region (Fig. 1B).
Re claim 18, Ahn teaches wherein the first transfer gate is closer to the photoelectric converter than the floating diffusion region, and the second transfer gate is closer to the floating diffusion region than the first transfer gate (Fig. 1B).
Allowable Subject Matter
Claims 2, 10-13 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: there is no teaching, suggestion, or motivation from the prior art of record, nor does the prior art of record otherwise make obvious the limitations of…
Re claim 2, …wherein the first transfer gate is disposed opposite to the second transfer gate with respect to an electron transfer pass center cross-section connecting the photoelectric converter and the floating diffusion region…
Re claims 10-13, …the second transfer gate overlaps the photoelectric converter at least partially in a plan view and contacts the floating diffusion region…
Re claim 16, …wherein a unit pixel including the source follower gate and the selection gate is different from a unit pixel including the reset gate…
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOLLY KAY REIDA whose telephone number is (571)272-4237. The examiner can normally be reached M-F 8:30-5:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408)918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOLLY K REIDA/Examiner, Art Unit 2899
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