DETAILED ACTION
This action is responsive to the following communications: the Request for Continued Examination (with claim amendment) filed on June 2, 2026.
Claims 1, 3-8, 10-15 and 17-20 are pending. Claims 2, 9 and 16 are canceled. Claims 1, 4, 8, 11, 15 and 17 are amended. Claims 1, 8 and 15 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 2, 2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-8, 10-15 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Luo et al. (US 20210149564; hereinafter “Luo 564”) in view of Luo et al. (US 20200043555; hereinafter “Luo 555”) and Liang et al. (US 20160172051).
Regarding independent claim 1, Luo 564 discloses a method [see Fig. 8: method 800, para. 85] comprising:
receiving a request to perform a program operation on a memory cell of a memory device [Fig. 8: step 802, a write command is issued and received by the memory device 110 (e.g., received from the host 105 via interface 111), para. 85];
determining a number of program erase cycles (PECs) associated with the memory device [Fig. 8: step 804, the memory controller 115 can identify a P/E cycle metric (Fig. 7: 714) which is indicative of a number of program-erase cycles performed by the memory device 110 within a selected time interval, para. 42 as well as para. 85];
determining a temperature of the memory device [Fig. 8: step 804, the memory controller 115 can identify a current temperature metric (Fig. 7: 716) which is indicative of temperature applicable to at least a monitored region of the memory device 110, para. 39, as well as para. 85];
identifying, from a plurality of entries in a programming adjustment data structure, an entry in which the temperature satisfies a temperature criterion and the number of PECs satisfies a PEC criterion, the entry comprising a gate voltage step adjustment value and a program verify level adjustment value [see Fig. 7, Luo 564 describes a selection of a memory trim set from a corresponding number of multiple candidate memory trim sets (e.g., memory trim sets # 1 through #9) based on the multiple temperature ranges 702, 704, and 706, as well as the multiple P/E cycle ranges 708, 710, and 712, para. 78-82. See Fig. 8: step 806, 810 and 814, one of operations 808, 812, and 816 is performed by the memory controller 115 to select one of the memory trim sets #1-#9, based on the temperature range and the P/E cycle range that are detected using the identified temperature and P/E cycle metrics, para. 86. The multiple candidate memory trim sets include multiple respective memory trim values (e.g., memory configuration parameters, such as program voltage step size, program pulse width, program verify level, etc., as discussed above) for performing the memory operation, para. 17];
retrieving, from the entry, the gate voltage step adjustment value and the program verify level adjustment value [the multiple candidate memory trim sets include multiple respective memory trim values (e.g., program voltage step size, program verify level) for performing the memory operation, para. 17. The memory trim values of the selected memory trim set are memory loaded, para. 86];
performing, using the adjusted gate voltage step and adjusted program verify level, the program operation on the memory cell [Fig. 8: step 808, 812 and 816, the memory trim values of the selected memory trim set are memory loaded, and the received write command is executed to write data into a storage region of the device 110 using the trim values for write operation parameters within the selected memory trim set, para. 86].
However, Luo 564 is silent with respect to adjusting a default gate voltage step by adding the gate voltage step adjustment value to the default gate voltage step to generate an adjusted gate voltage step, and adjusting a default program verify level by adding to the program verify level adjustment value to the default program verify level to generate an adjusted program verify level. Although Luo 564 does not disclose or suggest adjusting a default gate voltage step by adding the gate voltage step adjustment value to the default gate voltage step to generate an adjusted gate voltage step, the original disclosure does not limit the default gate voltage step at a specific value so under Broadest Reasonable Interpretation, the default gate voltage could be 0V and the claimed “gate voltage step adjustment value” is broad enough to include a trim value or delta used to adjust the programming step size.
Luo 555 further teaches that temperature compensation adjusts programming passes or trims based on current temperature and that P/E cycle information is used to modify the temperature compensation procedure to provide a more accurate starting and stepping voltage [para. 25-26 and 53]. Thus, Luo 555 provides motivation to modify the program voltage stepping behavior using temperature and P/E cycle information.
Besides that, Liang et al. teach adjusting a default program verify level by adding to the program verify level adjustment value to the default program verify level to generate an adjusted program verify level [see Fig. 7: step 702-706, the offset program verify levels may be determined using the programming temperature and/or P/E cycle associated with the solid-state memory, para. 48].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Luo 555 and Liang et al. to the teaching of Luo 564 such that modifying method for programming a cell using memory trim set based on a temperature and P/E cycles as taught by Luo 564 to use Liang et al.’s default-based adjustment and apply such compensation to increment programming behavior as taught by Luo 555 to obtain the predictable benefit of reducing bit error rate and improving memory device performance, reliability, and quality of service of the memory device.
Regarding claim 3, Luo 564 in combination with Luo 555 and Liang et al. teach the limitation with respect to claim 1.
Furthermore, Luo 555 disclose wherein performing, using the adjusted gate voltage step and adjusted program verify level, the program operation comprises:
incrementally applying, from an initial voltage value to a final voltage value, the adjusted gate voltage step to a programming voltage during a programming phase of the program operation [programming pulses can begin, for example, at or near 15V, and, in certain examples, can increase in magnitude during each programming pulse application, para. 53]; and
determining whether a threshold voltage of the memory cell has increased to the final voltage value by comparing the threshold voltage to the adjusted program verify level during a program verify phase of the program operation [see Fig. 5, the result of the programing is read (operation 525) and tested (decision 530) to determine whether the charge distribution in the cell has reached a verification level computed from the temperature compensation value written to the trim table, para. 68].
Regarding claim 4, Luo 564 in combination with Luo 555 and Liang et al. teach the limitation with respect to claim 1.
Furthermore, Luo 564 disclose wherein determining, based on the temperature and the number of PECs, the gate voltage step adjustment value and the program verify level adjustment value further comprises:
identifying, from the plurality of entries in the programming adjustment data structure, the entry in which the temperature satisfies the temperature criterion and the number of PECs satisfies the PEC criterion, the entry comprising the gate voltage step adjustment value and the program verify level adjustment [see Fig. 7, Luo 564 describes a selection of a memory trim set from a corresponding number of multiple candidate memory trim sets (e.g., memory trim sets # 1 through #9) based on the multiple temperature ranges 702, 704, and 706, as well as the multiple P/E cycle ranges 708, 710, and 712, para. 78-82. See Fig. 8: step 806, 810 and 814, one of operations 808, 812, and 816 is performed by the memory controller 115 to select one of the memory trim sets #1-#9, based on the temperature range and the P/E cycle range that are detected using the identified temperature and P/E cycle metrics, para. 86. The multiple candidate memory trim sets include multiple respective memory trim values (e.g., memory configuration parameters, such as program voltage step size, program pulse width, program verify level, etc., as discussed above) for performing the memory operation, para. 17].
Regarding claim 5, Luo 564 in combination with Luo 555 and Liang et al. teach the limitation with respect to claim 4.
Furthermore, Luo 564 disclose wherein each entry of the plurality of entries in the programming adjustment data structure is identified by satisfying the temperature criterion and the PEC criterion [see Fig. 8: step 806, 810 and 814, one of operations 808, 812, and 816 is performed by the memory controller 115 to select one of the memory trim sets #1-#9, based on the temperature range and the P/E cycle range that are detected using the identified temperature and P/E cycle metrics, para. 86].
Regarding claim 6, Luo 564 in combination with Luo 555 and Liang et al. teach the limitation with respect to claim 4.
Furthermore, Luo 564 disclose wherein the temperature criterion is satisfied if the temperature falls within a temperature threshold range associated with a respective entry [the temperature management module 160 is configured to maintain a temperature metric 162, which is indicative of temperature applicable to at least a monitored region of the memory device 110. In an example, the temperature metric 162 includes two or more status bits that indicate a temperature range for the region of the memory device. The temperature range can be one of a predetermined number (e.g., two or more) of temperature ranges, with each temperature range having a corresponding temperature metric with which it is associated, para. 39].
Regarding claim 7, Luo 564 in combination with Luo 555 and Liang et al. teach the limitation with respect to claim 4.
Furthermore, Luo 564 disclose wherein the PEC criterion is satisfied if the number of PECs falls within a PEC threshold range associated with a respective entry [the P/E cycle management module 170 is configured to maintain a P/E cycle metric 172, which is indicative of a number of program-erase cycles performed by the memory device 110 within a selected time interval. In an example, the P/E cycle metric 172 includes two or more status bits that indicate a P/E cycle range for the number of P/E cycles performed by the memory device within the selected time interval. The P/E cycle range can be one of a predetermined number (e.g., two or more) of P/E cycle ranges, with each P/E cycle range having a corresponding P/E cycle metric with which it is associated, para. 42].
Regarding independent claim 8, Luo 564 discloses a system [see Fig. 1] comprising:
a memory device [Fig. 1: 110, para. 26-27]; and
a processing device [Fig. 1: 115], operatively coupled to the memory device [para. 27], the processing device to perform operations comprising:
receiving a request to perform a program operation on a memory cell of a memory device [Fig. 8: step 802, a write command is issued and received by the memory device 110 (e.g., received from the host 105 via interface 111), para. 85];
determining a number of program erase cycles (PECs) associated with the memory device [Fig. 8: step 804, the memory controller 115 can identify a P/E cycle metric (Fig. 7: 714) which is indicative of a number of program-erase cycles performed by the memory device 110 within a selected time interval, para. 42 as well as para. 85];
determining a temperature of the memory device [Fig. 8: step 804, the memory controller 115 can identify a current temperature metric (Fig. 7: 716) which is indicative of temperature applicable to at least a monitored region of the memory device 110, para. 39, as well as para. 85];
identifying, from a plurality of entries in a programming adjustment data structure, an entry in which the temperature satisfies a temperature criterion and the number of PECs satisfies a PEC criterion, the entry comprising a gate voltage step adjustment value and a program verify level adjustment value [see Fig. 7, Luo 564 describes a selection of a memory trim set from a corresponding number of multiple candidate memory trim sets (e.g., memory trim sets # 1 through #9) based on the multiple temperature ranges 702, 704, and 706, as well as the multiple P/E cycle ranges 708, 710, and 712, para. 78-82. See Fig. 8: step 806, 810 and 814, one of operations 808, 812, and 816 is performed by the memory controller 115 to select one of the memory trim sets #1-#9, based on the temperature range and the P/E cycle range that are detected using the identified temperature and P/E cycle metrics, para. 86. The multiple candidate memory trim sets include multiple respective memory trim values (e.g., memory configuration parameters, such as program voltage step size, program pulse width, program verify level, etc., as discussed above) for performing the memory operation, para. 17];
retrieving, from the entry, the gate voltage step adjustment value and the program verify level adjustment value [the multiple candidate memory trim sets include multiple respective memory trim values (e.g., program voltage step size, program verify level) for performing the memory operation, para. 17. The memory trim values of the selected memory trim set are memory loaded, para. 86];
performing, using the adjusted gate voltage step and adjusted program verify level, the program operation on the memory cell [Fig. 8: step 808, 812 and 816, the memory trim values of the selected memory trim set are memory loaded, and the received write command is executed to write data into a storage region of the device 110 using the trim values for write operation parameters within the selected memory trim set, para. 86].
However, Luo 564 is silent with respect to adjusting a default gate voltage step by adding the gate voltage step adjustment value to the default gate voltage step to generate an adjusted gate voltage step, and adjusting a default program verify level by adding to the program verify level adjustment value to the default program verify level to generate an adjusted program verify level. Although Luo 564 does not disclose or suggest adjusting a default gate voltage step by adding the gate voltage step adjustment value to the default gate voltage step to generate an adjusted gate voltage step, the original disclosure does not limit the default gate voltage step at a specific value so under Broadest Reasonable Interpretation, the default gate voltage could be 0V and the claimed “gate voltage step adjustment value” is broad enough to include a trim value or delta used to adjust the programming step size.
Luo 555 further teaches that temperature compensation adjusts programming passes or trims based on current temperature and that P/E cycle information is used to modify the temperature compensation procedure to provide a more accurate starting and stepping voltage [para. 25-26 and 53]. Thus, Luo 555 provides motivation to modify the program voltage stepping behavior using temperature and P/E cycle information.
Besides that, Liang et al. teach adjusting a default program verify level by adding to the program verify level adjustment value to the default program verify level to generate an adjusted program verify level [see Fig. 7: step 702-706, the offset program verify levels may be determined using the programming temperature and/or P/E cycle associated with the solid-state memory, para. 48].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Luo 555 and Liang et al. to the teaching of Luo 564 such that modifying method for programming a cell using memory trim set based on a temperature and P/E cycles as taught by Luo 564 to use Liang et al.’s default-based adjustment and apply such compensation to increment programming behavior as taught by Luo 555 to obtain the predictable benefit of reducing bit error rate and improving memory device performance, reliability, and quality of service of the memory device.
Regarding claim 10, Luo 564 in combination with Luo 555 and Liang et al. teach the limitation with respect to claim 8.
Furthermore, Luo 555 disclose wherein performing, using the adjusted gate voltage step and adjusted program verify level, the program operation comprises:
incrementally applying, from an initial voltage value to a final voltage value, the adjusted gate voltage step to a programming voltage during a programming phase of the program operation [programming pulses can begin, for example, at or near 15V, and, in certain examples, can increase in magnitude during each programming pulse application, para. 53]; and
applying the adjusted program verify level during a program verify phase of the program operation [see Fig. 5: 520-530, the result of the programing is read (operation 525) and tested (decision 530) to determine whether the charge distribution in the cell has reached a verification level computed from the temperature compensation value written to the trim table, para. 68].
Regarding claim 11, Luo 564 in combination with Luo 555 and Liang et al. teach the limitation with respect to claim 8.
Furthermore, Luo 564 disclose wherein determining, based on the temperature and the number of PECs, the gate voltage step adjustment value and the program verify level adjustment value further comprises:
identifying, from the plurality of entries in the programming adjustment data structure, the entry in which the temperature satisfies the temperature criterion and the number of PECs satisfies the PEC criterion, the entry comprising the gate voltage step adjustment value and the program verify level adjustment [see Fig. 7, Luo 564 describes a selection of a memory trim set from a corresponding number of multiple candidate memory trim sets (e.g., memory trim sets # 1 through #9) based on the multiple temperature ranges 702, 704, and 706, as well as the multiple P/E cycle ranges 708, 710, and 712, para. 78-82. See Fig. 8: step 806, 810 and 814, one of operations 808, 812, and 816 is performed by the memory controller 115 to select one of the memory trim sets #1-#9, based on the temperature range and the P/E cycle range that are detected using the identified temperature and P/E cycle metrics, para. 86. The multiple candidate memory trim sets include multiple respective memory trim values (e.g., memory configuration parameters, such as program voltage step size, program pulse width, program verify level, etc., as discussed above) for performing the memory operation, para. 17].
Regarding claim 12, Luo 564 in combination with Luo 555 and Liang et al. teach the limitation with respect to claim 11.
Furthermore, Luo 564 disclose wherein each entry of the plurality of entries in the programming adjustment data structure is identified by satisfying the temperature criterion and the PEC criterion [see Fig. 8: step 806, 810 and 814, one of operations 808, 812, and 816 is performed by the memory controller 115 to select one of the memory trim sets #1-#9, based on the temperature range and the P/E cycle range that are detected using the identified temperature and P/E cycle metrics, para. 86].
Regarding claim 13, Luo 564 in combination with Luo 555 and Liang et al. teach the limitation with respect to claim 11.
Furthermore, Luo 564 disclose wherein the temperature criterion is satisfied if the temperature falls within a temperature threshold range associated with a respective entry [the temperature management module 160 is configured to maintain a temperature metric 162, which is indicative of temperature applicable to at least a monitored region of the memory device 110. In an example, the temperature metric 162 includes two or more status bits that indicate a temperature range for the region of the memory device. The temperature range can be one of a predetermined number (e.g., two or more) of temperature ranges, with each temperature range having a corresponding temperature metric with which it is associated, para. 39].
Regarding claim 14, Luo 564 in combination with Luo 555 and Liang et al. teach the limitation with respect to claim 11.
Furthermore, Luo 564 disclose wherein the PEC criterion is satisfied if the number of PECs falls within a PEC threshold range associated with a respective entry [the P/E cycle management module 170 is configured to maintain a P/E cycle metric 172, which is indicative of a number of program-erase cycles performed by the memory device 110 within a selected time interval. In an example, the P/E cycle metric 172 includes two or more status bits that indicate a P/E cycle range for the number of P/E cycles performed by the memory device within the selected time interval. The P/E cycle range can be one of a predetermined number (e.g., two or more) of P/E cycle ranges, with each P/E cycle range having a corresponding P/E cycle metric with which it is associated, para. 42].
Regarding independent claim 15, Luo 564 discloses a non-transitory computer readable storage medium including instructions that, when executed by a processing device [see Fig. 10, para. 89=92], cause the processing device to perform a method comprising:
receiving a request to perform a program operation on a memory cell of a memory device [Fig. 8: step 802, a write command is issued and received by the memory device 110 (e.g., received from the host 105 via interface 111), para. 85];
determining a number of program erase cycles (PECs) associated with the memory device [Fig. 8: step 804, the memory controller 115 can identify a P/E cycle metric (Fig. 7: 714) which is indicative of a number of program-erase cycles performed by the memory device 110 within a selected time interval, para. 42 as well as para. 85];
determining a temperature of the memory device [Fig. 8: step 804, the memory controller 115 can identify a current temperature metric (Fig. 7: 716) which is indicative of temperature applicable to at least a monitored region of the memory device 110, para. 39, as well as para. 85];
identifying, from a plurality of entries in a programming adjustment data structure, an entry in which the temperature satisfies a temperature criterion and the number of PECs satisfies a PEC criterion, the entry comprising a gate voltage step adjustment value and a program verify level adjustment value [see Fig. 7, Luo 564 describes a selection of a memory trim set from a corresponding number of multiple candidate memory trim sets (e.g., memory trim sets # 1 through #9) based on the multiple temperature ranges 702, 704, and 706, as well as the multiple P/E cycle ranges 708, 710, and 712, para. 78-82. See Fig. 8: step 806, 810 and 814, one of operations 808, 812, and 816 is performed by the memory controller 115 to select one of the memory trim sets #1-#9, based on the temperature range and the P/E cycle range that are detected using the identified temperature and P/E cycle metrics, para. 86. The multiple candidate memory trim sets include multiple respective memory trim values (e.g., memory configuration parameters, such as program voltage step size, program pulse width, program verify level, etc., as discussed above) for performing the memory operation, para. 17];
retrieving, from the entry, the gate voltage step adjustment value and the program verify level adjustment value [the multiple candidate memory trim sets include multiple respective memory trim values (e.g., program voltage step size, program verify level) for performing the memory operation, para. 17. The memory trim values of the selected memory trim set are memory loaded, para. 86];
performing, using the adjusted gate voltage step and adjusted program verify level, the program operation on the memory cell [Fig. 8: step 808, 812 and 816, the memory trim values of the selected memory trim set are memory loaded, and the received write command is executed to write data into a storage region of the device 110 using the trim values for write operation parameters within the selected memory trim set, para. 86].
However, Luo 564 is silent with respect to adjusting a default gate voltage step by adding the gate voltage step adjustment value to the default gate voltage step to generate an adjusted gate voltage step, and adjusting a default program verify level by adding to the program verify level adjustment value to the default program verify level to generate an adjusted program verify level. Although Luo 564 does not disclose or suggest adjusting a default gate voltage step by adding the gate voltage step adjustment value to the default gate voltage step to generate an adjusted gate voltage step, the original disclosure does not limit the default gate voltage step at a specific value so under Broadest Reasonable Interpretation, the default gate voltage could be 0V and the claimed “gate voltage step adjustment value” is broad enough to include a trim value or delta used to adjust the programming step size.
Luo 555 further teaches that temperature compensation adjusts programming passes or trims based on current temperature and that P/E cycle information is used to modify the temperature compensation procedure to provide a more accurate starting and stepping voltage [para. 25-26 and 53]. Thus, Luo 555 provides motivation to modify the program voltage stepping behavior using temperature and P/E cycle information.
Besides that, Liang et al. teach adjusting a default program verify level by adding to the program verify level adjustment value to the default program verify level to generate an adjusted program verify level [see Fig. 7: step 702-706, the offset program verify levels may be determined using the programming temperature and/or P/E cycle associated with the solid-state memory, para. 48].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Luo 555 and Liang et al. to the teaching of Luo 564 such that modifying method for programming a cell using memory trim set based on a temperature and P/E cycles as taught by Luo 564 to use Liang et al.’s default-based adjustment and apply such compensation to increment programming behavior as taught by Luo 555 to obtain the predictable benefit of reducing bit error rate and improving memory device performance, reliability, and quality of service of the memory device.
Regarding claim 17, Luo 564 in combination with Luo 555 and Liang et al. teach the limitation with respect to claim 15.
Furthermore, Luo 564 disclose wherein determining, based on the temperature and the number of PECs, the gate voltage step adjustment value and the program verify level adjustment value further comprises:
identifying, from the plurality of entries in the programming adjustment data structure, the entry in which the temperature satisfies the temperature criterion and the number of PECs satisfies the PEC criterion, the entry comprising the gate voltage step adjustment value and the program verify level adjustment [see Fig. 7, Luo 564 describes a selection of a memory trim set from a corresponding number of multiple candidate memory trim sets (e.g., memory trim sets # 1 through #9) based on the multiple temperature ranges 702, 704, and 706, as well as the multiple P/E cycle ranges 708, 710, and 712, para. 78-82. See Fig. 8: step 806, 810 and 814, one of operations 808, 812, and 816 is performed by the memory controller 115 to select one of the memory trim sets #1-#9, based on the temperature range and the P/E cycle range that are detected using the identified temperature and P/E cycle metrics, para. 86. The multiple candidate memory trim sets include multiple respective memory trim values (e.g., memory configuration parameters, such as program voltage step size, program pulse width, program verify level, etc., as discussed above) for performing the memory operation, para. 17].
Regarding claim 18, Luo 564 in combination with Luo 555 and Liang et al. teach the limitation with respect to claim 17.
Furthermore, Luo 564 disclose wherein each entry of the plurality of entries in the programming adjustment data structure is identified by satisfying the temperature criterion and the PEC criterion [see Fig. 8: step 806, 810 and 814, one of operations 808, 812, and 816 is performed by the memory controller 115 to select one of the memory trim sets #1-#9, based on the temperature range and the P/E cycle range that are detected using the identified temperature and P/E cycle metrics, para. 86].
Regarding claim 19, Luo 564 in combination with Luo 555 and Liang et al. teach the limitation with respect to claim 18.
Furthermore, Luo 564 disclose wherein the temperature criterion is satisfied if the temperature falls within a temperature threshold range associated with a respective entry [the temperature management module 160 is configured to maintain a temperature metric 162, which is indicative of temperature applicable to at least a monitored region of the memory device 110. In an example, the temperature metric 162 includes two or more status bits that indicate a temperature range for the region of the memory device. The temperature range can be one of a predetermined number (e.g., two or more) of temperature ranges, with each temperature range having a corresponding temperature metric with which it is associated, para. 39].
Regarding claim 20, Luo 564 in combination with Luo 555 and Liang et al. teach the limitation with respect to claim 18.
Furthermore, Luo 564 disclose wherein the PEC criterion is satisfied if the number of PECs falls within a PEC threshold range associated with a respective entry [the P/E cycle management module 170 is configured to maintain a P/E cycle metric 172, which is indicative of a number of program-erase cycles performed by the memory device 110 within a selected time interval. In an example, the P/E cycle metric 172 includes two or more status bits that indicate a P/E cycle range for the number of P/E cycles performed by the memory device within the selected time interval. The P/E cycle range can be one of a predetermined number (e.g., two or more) of P/E cycle ranges, with each P/E cycle range having a corresponding P/E cycle metric with which it is associated, para. 42].
Response to Arguments
Applicant's arguments filed on 05/13/2026 with respect to claims 1, 3-8, 10-15 and 17-20 have been fully considered but they are not deemed persuasive.
With respect to independent claim 1, Applicant asserts that the Office Action does not allege that Luo 555 teaches or suggests determining a gate voltage step adjustment value from the P/E cycle that can be added to a default gate voltage step to modify the default gate voltage step. There is no indication of how the Office Action interprets Luo 555 as teaching any separately obtained or determined adjustment value that is added to a default gate voltage step, Moreover, Applicant asserts that Liang et al. do not teach or suggest the above referenced features of claim 1 and is not relied upon for this purpose in the Office Action, see Applicant's Remarks pages 10-11. This particular remark is not considered persuasive.
The rejection of claim 1 is based on the combined teachings of the applied references, not Luo 555 alone. One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references [see MPEP 2145 IV].
Luo 564 teaches selecting a memory trim from multiple candidate trim sets based on both a temperature metric and a P/E cycle metric, where the selected trim set includes memory trim values for write operation parameters, including program voltage step size and program verify level. Moreover, the original disclosure does not limit the default gate voltage step at a specific value so under Broadest Reasonable Interpretation, the default gate voltage could be 0V and the claimed “gate voltage step adjustment value” is broad enough to include a trim value or delta used to adjust the programming step size.
Luo 555 further teaches that temperature compensation adjusts programming passes or trims based on current temperature and that P/E cycle information is used to modify the temperature compensation procedure to provide a more accurate starting and stepping voltage. Thus, Luo 555 provides motivation to modify the program voltage stepping behavior using temperature and P/E cycle information.
Besides that, Liang et al. teach the known additive offset implementation for memory programming parameters, including adding offset program verify levels to default program verify levels based on programming temperature and P/E cycle. Liang et al. further teach use of a lookup table to identify and retrieve offset values based on temperature and P/E cycle condition data.
Accordingly, it would have been obvious to a person of ordinary skill in the art to implement the program voltage step size trim of Luo 564, as motivated by Luo 555, in the same additive offset manner taught by Liang et al., namely by adding a gate voltage step adjustment value to a default gate voltage step to generate an adjusted gate voltage step and by adding a program verify level adjustment value to a default program verify level to generate an adjusted program verify level, in order to obtain the predictable benefit of reducing bit error rate and improving reliability of the memory device.
For the above reasons, the applied rejection is considered proper and maintained. The independent claims 8 and 15 were argued for substantially the same reason, thus the arguments are not persuasive for the same reason.
Conclusion
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/DUY H LUONG/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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