DETAILED ACTION
This action is responsive to the following communications: the Amendment filed on December 11, 2025 and the Provisional application No. 63/486,851 filed on February 24, 2023.
Claims 1, 3-8, 10-15 and 17-20 are pending. Claims 2, 9 and 16 are canceled. Claims 1, 3, 5, 8, 10, 12, 15 and 18 are amended. Claims 1, 8 and 15 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1, 8 and 15 are objected to because of the following informalities:
In claim 1, line 10, “a program verify level adjustment” should be --a program verify level adjustment value--.
In claim 1, line 11, “the program verify level adjustment” should be --the program verify level adjustment value--.
In claim 8, line 13, “a program verify level adjustment” should be --a program verify level adjustment value--.
In claim 8, line 14, “the program verify level adjustment” should be --the program verify level adjustment value--.
In claim 15, line 12, “a program verify level adjustment” should be --a program verify level adjustment value--.
In claim 15, line 13, “the program verify level adjustment” should be --the program verify level adjustment value--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-8, 10-15 and 17-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Each of claims 1, 8 and 15 recite the limitation "the adjusted gate voltage step and adjusted program verify level" in the last 2 lines of each claim. There is insufficient antecedent basis for this limitation in the claims.
Each of claims 4, 11 and 17 recite “a plurality of entries”, “a programming adjustment data structure”, “an entry”, “a temperature criterion” and “a PEC criterion,” however their antecedent claims (i.e., claims 1, 8 and 15, respectively) already recite “a plurality of entries”, “a programming adjustment data structure”, “an entry”, “a temperature criterion” and “a PEC criterion.” In other words, the use of “a plurality of entries”, “a programming adjustment data structure”, “an entry”, “a temperature criterion” and “a PEC criterion” in further dependent claims 4, 11 and 17 creates an antecedent basis problem because it would be unclear whether dependent claims 4, 11 and 17 require an additional “plurality of entries”, “programming adjustment data structure”, “entry”, “temperature criterion” and “PEC criterion” or whether applicant simply intended to relate back to claim 1’s, 8’s and 15’s “plurality of entries”, “programming adjustment data structure”, “entry”, “temperature criterion” and “PEC criterion.” Claims 5-7, 12-14 and 18-20 are rejected for inheriting this issue from claims 4, 11 and 17 because they do not resolve the antecedent basis problem.
For purposes of compact prosecution (MPEP 2173.06(II)), claims 4, 11, and 17 are interpreted as --the plurality of entries--, --the programming adjustment data structure--, --the entry--, --the temperature criterion-- and --the PEC criterion--, thereby relating-back to an antecedent in claims 1, 8 and 15. Correction consistent with this interpretation is required.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 4, 11 and 17 rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends (i.e., claims 1, 8 and 15, respectively), or for failing to include all the limitations of the claim upon which it depends.
With respect to the further limit the subject matter requirement, claims 4, 11 and 17 do not add any additional limitation beyond claims 1, 8 and 15, respectively. In particular, claims 1, 8 and 15 already require “determining a number of program erase cycles (PECs) associated with the memory device; determining a temperature of the memory device; identifying, from a plurality of entries in a programming adjustment data structure, an entry in which the temperature satisfies a temperature criterion and the number of PECs satisfies a PEC criterion, the entry comprising a gate voltage step adjustment value and a program verify level adjustment”. Claims 4, 11 and 17 merely restates this same “identifying, from a plurality of entries in a programming adjustment data structure, an entry in which the temperature satisfies a temperature criterion and the number of PECs satisfies a PEC criterion, the entry comprising the gate voltage step adjustment value and the program verify level adjustment” requirement as part of the “determining” step, without adding any additional structural or procedural constraint that would narrow claims 1, 8 and 15. Accordingly, claims 4, 11 and 17 are coextensive with and fails to further limit, claims 4, 11 and 17. Therefore, claims 4, 11 and 17 are not in proper dependent form under 35 U.S.C. 112(d).
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-8, 10-15 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Luo et al. (US 20210149564; hereinafter “Luo 564”) in view of Luo et al. (US 20200043555; hereinafter “Luo 555”) and Liang et al. (US 20160172051).
Regarding independent claim 1, Luo 564 discloses a method [see Fig. 8: method 800, para. 85] comprising:
receiving a request to perform a program operation on a memory cell of a memory device [Fig. 8: step 802, a write command is issued and received by the memory device 110 (e.g., received from the host 105 via interface 111), para. 85];
determining a number of program erase cycles (PECs) associated with the memory device [Fig. 8: step 804, the memory controller 115 can identify a P/E cycle metric (Fig. 7: 714) which is indicative of a number of program-erase cycles performed by the memory device 110 within a selected time interval, para. 42 as well as para. 85];
determining a temperature of the memory device [Fig. 8: step 804, the memory controller 115 can identify a current temperature metric (Fig. 7: 716) which is indicative of temperature applicable to at least a monitored region of the memory device 110, para. 39, as well as para. 85];
identifying, from a plurality of entries in a programming adjustment data structure, an entry in which the temperature satisfies a temperature criterion and the number of PECs satisfies a PEC criterion, the entry comprising a gate voltage step adjustment value and a program verify level adjustment [see Fig. 7, Luo 564 describes a selection of a memory trim set from a corresponding number of multiple candidate memory trim sets (e.g., memory trim sets # 1 through #9) based on the multiple temperature ranges 702, 704, and 706, as well as the multiple P/E cycle ranges 708, 710, and 712, para. 78-82. See Fig. 8: step 806, 810 and 814, one of operations 808, 812, and 816 is performed by the memory controller 115 to select one of the memory trim sets #1-#9, based on the temperature range and the P/E cycle range that are detected using the identified temperature and P/E cycle metrics, para. 86. The multiple candidate memory trim sets include multiple respective memory trim values (e.g., memory configuration parameters, such as program voltage step size, program pulse width, program verify level, etc., as discussed above) for performing the memory operation, para. 17];
retrieving, from the entry, the gate voltage step adjustment value and the program verify level adjustment [the multiple candidate memory trim sets include multiple respective memory trim values (e.g., program voltage step size, program verify level) for performing the memory operation, para. 17. The memory trim values of the selected memory trim set are memory loaded, para. 86];
performing, using the adjusted gate voltage step and adjusted program verify level, the program operation on the memory cell [Fig. 8: step 808, 812 and 816, the memory trim values of the selected memory trim set are memory loaded, and the received write command is executed to write data into a storage region of the device 110 using the trim values for write operation parameters within the selected memory trim set, para. 86].
However, Luo 564 is silent with respect to adjusting, based on the gate voltage step adjustment value, a default gate voltage step and adjusting, based on the program verify level adjustment value, a default program verify level.
Luo 555 teaches adjusting, based on the gate voltage step adjustment value, a default gate voltage step [tracking the P/E cycles for the cell being programmed and using this value to modify the temperature compensation procedure can result in a more accurate starting and stepping voltage to achieve the target charge distribution, para. 25. The programming pulse can continue until the target charge distribution passes the verification level, para. 26. Programming pulses can begin, for example, at or near 15V, and, in certain examples, can increase in magnitude during each programming pulse application, para. 53].
Besides that, Liang et al. teach adjusting, based the program verify level adjustment value, a default program verify level [see Fig. 7: step 702-706, the offset program verify levels may be determined using the programming temperature and/or P/E cycle associated with the solid-state memory, para. 48].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Luo 555 and Liang et al. to the teaching of Luo 564 such that modifying method for programming a cell using memory trim set based on a temperature and P/E cycles as taught by Luo 564 to implement Luo 555’s default gate voltage step plus offset value scheme and Liang et al.’s default program verify level plus offset value scheme to obtain the predictable benefit of reducing bit error rate and improving memory device performance, reliability, and quality of service of the memory device.
Regarding claim 3, Luo 564 in combination with Luo 555 and Liang et al. teach the limitation with respect to claim 1.
Furthermore, Luo 555 disclose wherein performing, using the adjusted gate voltage step and adjusted program verify level, the program operation comprises:
incrementally applying, from an initial voltage value to a final voltage value, the adjusted gate voltage step to a programming voltage during a programming phase of the program operation [programming pulses can begin, for example, at or near 15V, and, in certain examples, can increase in magnitude during each programming pulse application, para. 53]; and
determining whether a threshold voltage of the memory cell has increased to the final voltage value by comparing the threshold voltage to the adjusted program verify level during a program verify phase of the program operation [see Fig. 5, the result of the programing is read (operation 525) and tested (decision 530) to determine whether the charge distribution in the cell has reached a verification level computed from the temperature compensation value written to the trim table, para. 68].
Regarding claim 4, Luo 564 in combination with Luo 555 and Liang et al. teach the limitation with respect to claim 1.
Furthermore, Luo 564 disclose wherein determining, based on the temperature and the number of PECs, the gate voltage step adjustment value and the program verify level adjustment value further comprises:
identifying, from a plurality of entries in a programming adjustment data structure, an entry in which the temperature satisfies a temperature criterion and the number of PECs satisfies a PEC criterion, the entry comprising the gate voltage step adjustment value and the program verify level adjustment [see Fig. 7, Luo 564 describes a selection of a memory trim set from a corresponding number of multiple candidate memory trim sets (e.g., memory trim sets # 1 through #9) based on the multiple temperature ranges 702, 704, and 706, as well as the multiple P/E cycle ranges 708, 710, and 712, para. 78-82. See Fig. 8: step 806, 810 and 814, one of operations 808, 812, and 816 is performed by the memory controller 115 to select one of the memory trim sets #1-#9, based on the temperature range and the P/E cycle range that are detected using the identified temperature and P/E cycle metrics, para. 86. The multiple candidate memory trim sets include multiple respective memory trim values (e.g., memory configuration parameters, such as program voltage step size, program pulse width, program verify level, etc., as discussed above) for performing the memory operation, para. 17].
Regarding claim 5, Luo 564 in combination with Luo 555 and Liang et al. teach the limitation with respect to claim 4.
Furthermore, Luo 564 disclose wherein each entry of the plurality of entries in the programming adjustment data structure is identified by satisfying the temperature criterion and the PEC criterion [see Fig. 8: step 806, 810 and 814, one of operations 808, 812, and 816 is performed by the memory controller 115 to select one of the memory trim sets #1-#9, based on the temperature range and the P/E cycle range that are detected using the identified temperature and P/E cycle metrics, para. 86].
Regarding claim 6, Luo 564 in combination with Luo 555 and Liang et al. teach the limitation with respect to claim 4.
Furthermore, Luo 564 disclose wherein the temperature criterion is satisfied if the temperature falls within a temperature threshold range associated with a respective entry [the temperature management module 160 is configured to maintain a temperature metric 162, which is indicative of temperature applicable to at least a monitored region of the memory device 110. In an example, the temperature metric 162 includes two or more status bits that indicate a temperature range for the region of the memory device. The temperature range can be one of a predetermined number (e.g., two or more) of temperature ranges, with each temperature range having a corresponding temperature metric with which it is associated, para. 39].
Regarding claim 7, Luo 564 in combination with Luo 555 and Liang et al. teach the limitation with respect to claim 4.
Furthermore, Luo 564 disclose wherein the PEC criterion is satisfied if the number of PECs falls within a PEC threshold range associated with a respective entry [the P/E cycle management module 170 is configured to maintain a P/E cycle metric 172, which is indicative of a number of program-erase cycles performed by the memory device 110 within a selected time interval. In an example, the P/E cycle metric 172 includes two or more status bits that indicate a P/E cycle range for the number of P/E cycles performed by the memory device within the selected time interval. The P/E cycle range can be one of a predetermined number (e.g., two or more) of P/E cycle ranges, with each P/E cycle range having a corresponding P/E cycle metric with which it is associated, para. 42].
Regarding independent claim 8, Luo 564 discloses a system [see Fig. 1] comprising:
a memory device [Fig. 1: 110, para. 26-27]; and
a processing device [Fig. 1: 115], operatively coupled to the memory device [para. 27], the processing device to perform operations comprising:
receiving a request to perform a program operation on a memory cell of a memory device [Fig. 8: step 802, a write command is issued and received by the memory device 110 (e.g., received from the host 105 via interface 111), para. 85];
determining a number of program erase cycles (PECs) associated with the memory device [Fig. 8: step 804, the memory controller 115 can identify a P/E cycle metric (Fig. 7: 714) which is indicative of a number of program-erase cycles performed by the memory device 110 within a selected time interval, para. 42 as well as para. 85];
determining a temperature of the memory device [Fig. 8: step 804, the memory controller 115 can identify a current temperature metric (Fig. 7: 716) which is indicative of temperature applicable to at least a monitored region of the memory device 110, para. 39, as well as para. 85];
identifying, from a plurality of entries in a programming adjustment data structure, an entry in which the temperature satisfies a temperature criterion and the number of PECs satisfies a PEC criterion, the entry comprising a gate voltage step adjustment value and a program verify level adjustment [see Fig. 7, Luo 564 describes a selection of a memory trim set from a corresponding number of multiple candidate memory trim sets (e.g., memory trim sets # 1 through #9) based on the multiple temperature ranges 702, 704, and 706, as well as the multiple P/E cycle ranges 708, 710, and 712, para. 78-82. See Fig. 8: step 806, 810 and 814, one of operations 808, 812, and 816 is performed by the memory controller 115 to select one of the memory trim sets #1-#9, based on the temperature range and the P/E cycle range that are detected using the identified temperature and P/E cycle metrics, para. 86. The multiple candidate memory trim sets include multiple respective memory trim values (e.g., memory configuration parameters, such as program voltage step size, program pulse width, program verify level, etc., as discussed above) for performing the memory operation, para. 17];
retrieving, from the entry, the gate voltage step adjustment value and the program verify level adjustment [the multiple candidate memory trim sets include multiple respective memory trim values (e.g., program voltage step size, program verify level) for performing the memory operation, para. 17. The memory trim values of the selected memory trim set are memory loaded, para. 86];
performing, using the adjusted gate voltage step and adjusted program verify level, the program operation on the memory cell [Fig. 8: step 808, 812 and 816, the memory trim values of the selected memory trim set are memory loaded, and the received write command is executed to write data into a storage region of the device 110 using the trim values for write operation parameters within the selected memory trim set, para. 86].
However, Luo 564 is silent with respect to adjusting, based on the gate voltage step adjustment value, a default gate voltage step and adjusting, based on the program verify level adjustment value, a default program verify level.
Luo 555 teaches adjusting, based on the gate voltage step adjustment value, a default gate voltage step [tracking the P/E cycles for the cell being programmed and using this value to modify the temperature compensation procedure can result in a more accurate starting and stepping voltage to achieve the target charge distribution, para. 25. The programming pulse can continue until the target charge distribution passes the verification level, para. 26. Programming pulses can begin, for example, at or near 15V, and, in certain examples, can increase in magnitude during each programming pulse application, para. 53].
Besides that, Liang et al. teach adjusting, based the program verify level adjustment value, a default program verify level [see Fig. 7: step 702-706, the offset program verify levels may be determined using the programming temperature and/or P/E cycle associated with the solid-state memory, para. 48].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Luo 555 and Liang et al. to the teaching of Luo 564 such that modifying method for programming a cell using memory trim set based on a temperature and P/E cycles as taught by Luo 564 to implement Luo 555’s default gate voltage step plus offset value scheme and Liang et al.’s default program verify level plus offset value scheme to obtain the predictable benefit of reducing bit error rate and improving memory device performance, reliability, and quality of service of the memory device.
Regarding claim 10, Luo 564 in combination with Luo 555 and Liang et al. teach the limitation with respect to claim 8.
Furthermore, Luo 555 disclose wherein performing, using the adjusted gate voltage step and adjusted program verify level, the program operation comprises:
incrementally applying, from an initial voltage value to a final voltage value, the adjusted gate voltage step to a programming voltage during a programming phase of the program operation [programming pulses can begin, for example, at or near 15V, and, in certain examples, can increase in magnitude during each programming pulse application, para. 53]; and
applying the adjusted program verify level during a program verify phase of the program operation [see Fig. 5: 520-530, the result of the programing is read (operation 525) and tested (decision 530) to determine whether the charge distribution in the cell has reached a verification level computed from the temperature compensation value written to the trim table, para. 68].
Regarding claim 11, Luo 564 in combination with Luo 555 and Liang et al. teach the limitation with respect to claim 8.
Furthermore, Luo 564 disclose wherein determining, based on the temperature and the number of PECs, the gate voltage step adjustment value and the program verify level adjustment value further comprises:
identifying, from a plurality of entries in a programming adjustment data structure, an entry in which the temperature satisfies a temperature criterion and the number of PECs satisfies a PEC criterion, the entry comprising the gate voltage step adjustment value and the program verify level adjustment [see Fig. 7, Luo 564 describes a selection of a memory trim set from a corresponding number of multiple candidate memory trim sets (e.g., memory trim sets # 1 through #9) based on the multiple temperature ranges 702, 704, and 706, as well as the multiple P/E cycle ranges 708, 710, and 712, para. 78-82. See Fig. 8: step 806, 810 and 814, one of operations 808, 812, and 816 is performed by the memory controller 115 to select one of the memory trim sets #1-#9, based on the temperature range and the P/E cycle range that are detected using the identified temperature and P/E cycle metrics, para. 86. The multiple candidate memory trim sets include multiple respective memory trim values (e.g., memory configuration parameters, such as program voltage step size, program pulse width, program verify level, etc., as discussed above) for performing the memory operation, para. 17].
Regarding claim 12, Luo 564 in combination with Luo 555 and Liang et al. teach the limitation with respect to claim 11.
Furthermore, Luo 564 disclose wherein each entry of the plurality of entries in the programming adjustment data structure is identified by satisfying the temperature criterion and the PEC criterion [see Fig. 8: step 806, 810 and 814, one of operations 808, 812, and 816 is performed by the memory controller 115 to select one of the memory trim sets #1-#9, based on the temperature range and the P/E cycle range that are detected using the identified temperature and P/E cycle metrics, para. 86].
Regarding claim 13, Luo 564 in combination with Luo 555 and Liang et al. teach the limitation with respect to claim 11.
Furthermore, Luo 564 disclose wherein the temperature criterion is satisfied if the temperature falls within a temperature threshold range associated with a respective entry [the temperature management module 160 is configured to maintain a temperature metric 162, which is indicative of temperature applicable to at least a monitored region of the memory device 110. In an example, the temperature metric 162 includes two or more status bits that indicate a temperature range for the region of the memory device. The temperature range can be one of a predetermined number (e.g., two or more) of temperature ranges, with each temperature range having a corresponding temperature metric with which it is associated, para. 39].
Regarding claim 14, Luo 564 in combination with Luo 555 and Liang et al. teach the limitation with respect to claim 11.
Furthermore, Luo 564 disclose wherein the PEC criterion is satisfied if the number of PECs falls within a PEC threshold range associated with a respective entry [the P/E cycle management module 170 is configured to maintain a P/E cycle metric 172, which is indicative of a number of program-erase cycles performed by the memory device 110 within a selected time interval. In an example, the P/E cycle metric 172 includes two or more status bits that indicate a P/E cycle range for the number of P/E cycles performed by the memory device within the selected time interval. The P/E cycle range can be one of a predetermined number (e.g., two or more) of P/E cycle ranges, with each P/E cycle range having a corresponding P/E cycle metric with which it is associated, para. 42].
Regarding independent claim 15, Luo 564 discloses a non-transitory computer readable storage medium including instructions that, when executed by a processing device [see Fig. 10, para. 89=92], cause the processing device to perform a method comprising:
receiving a request to perform a program operation on a memory cell of a memory device [Fig. 8: step 802, a write command is issued and received by the memory device 110 (e.g., received from the host 105 via interface 111), para. 85];
determining a number of program erase cycles (PECs) associated with the memory device [Fig. 8: step 804, the memory controller 115 can identify a P/E cycle metric (Fig. 7: 714) which is indicative of a number of program-erase cycles performed by the memory device 110 within a selected time interval, para. 42 as well as para. 85];
determining a temperature of the memory device [Fig. 8: step 804, the memory controller 115 can identify a current temperature metric (Fig. 7: 716) which is indicative of temperature applicable to at least a monitored region of the memory device 110, para. 39, as well as para. 85];
identifying, from a plurality of entries in a programming adjustment data structure, an entry in which the temperature satisfies a temperature criterion and the number of PECs satisfies a PEC criterion, the entry comprising a gate voltage step adjustment value and a program verify level adjustment [see Fig. 7, Luo 564 describes a selection of a memory trim set from a corresponding number of multiple candidate memory trim sets (e.g., memory trim sets # 1 through #9) based on the multiple temperature ranges 702, 704, and 706, as well as the multiple P/E cycle ranges 708, 710, and 712, para. 78-82. See Fig. 8: step 806, 810 and 814, one of operations 808, 812, and 816 is performed by the memory controller 115 to select one of the memory trim sets #1-#9, based on the temperature range and the P/E cycle range that are detected using the identified temperature and P/E cycle metrics, para. 86. The multiple candidate memory trim sets include multiple respective memory trim values (e.g., memory configuration parameters, such as program voltage step size, program pulse width, program verify level, etc., as discussed above) for performing the memory operation, para. 17];
retrieving, from the entry, the gate voltage step adjustment value and the program verify level adjustment [the multiple candidate memory trim sets include multiple respective memory trim values (e.g., program voltage step size, program verify level) for performing the memory operation, para. 17. The memory trim values of the selected memory trim set are memory loaded, para. 86];
performing, using the adjusted gate voltage step and adjusted program verify level, the program operation on the memory cell [Fig. 8: step 808, 812 and 816, the memory trim values of the selected memory trim set are memory loaded, and the received write command is executed to write data into a storage region of the device 110 using the trim values for write operation parameters within the selected memory trim set, para. 86].
However, Luo 564 is silent with respect to adjusting, based on the gate voltage step adjustment value, a default gate voltage step and adjusting, based on the program verify level adjustment value, a default program verify level.
Luo 555 teaches adjusting, based on the gate voltage step adjustment value, a default gate voltage step [tracking the P/E cycles for the cell being programmed and using this value to modify the temperature compensation procedure can result in a more accurate starting and stepping voltage to achieve the target charge distribution, para. 25. The programming pulse can continue until the target charge distribution passes the verification level, para. 26. Programming pulses can begin, for example, at or near 15V, and, in certain examples, can increase in magnitude during each programming pulse application, para. 53].
Besides that, Liang et al. teach adjusting, based the program verify level adjustment value, a default program verify level [see Fig. 7: step 702-706, the offset program verify levels may be determined using the programming temperature and/or P/E cycle associated with the solid-state memory, para. 48].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Luo 555 and Liang et al. to the teaching of Luo 564 such that modifying method for programming a cell using memory trim set based on a temperature and P/E cycles as taught by Luo 564 to implement Luo 555’s default gate voltage step plus offset value scheme and Liang et al.’s default program verify level plus offset value scheme to obtain the predictable benefit of reducing bit error rate and improving memory device performance, reliability, and quality of service of the memory device.
Regarding claim 17, Luo 564 in combination with Luo 555 and Liang et al. teach the limitation with respect to claim 15.
Furthermore, Luo 564 disclose wherein determining, based on the temperature and the number of PECs, the gate voltage step adjustment value and the program verify level adjustment value further comprises:
identifying, from a plurality of entries in a programming adjustment data structure, an entry in which the temperature satisfies a temperature criterion and the number of PECs satisfies a PEC criterion, the entry comprising the gate voltage step adjustment value and the program verify level adjustment [see Fig. 7, Luo 564 describes a selection of a memory trim set from a corresponding number of multiple candidate memory trim sets (e.g., memory trim sets # 1 through #9) based on the multiple temperature ranges 702, 704, and 706, as well as the multiple P/E cycle ranges 708, 710, and 712, para. 78-82. See Fig. 8: step 806, 810 and 814, one of operations 808, 812, and 816 is performed by the memory controller 115 to select one of the memory trim sets #1-#9, based on the temperature range and the P/E cycle range that are detected using the identified temperature and P/E cycle metrics, para. 86. The multiple candidate memory trim sets include multiple respective memory trim values (e.g., memory configuration parameters, such as program voltage step size, program pulse width, program verify level, etc., as discussed above) for performing the memory operation, para. 17].
Regarding claim 18, Luo 564 in combination with Luo 555 and Liang et al. teach the limitation with respect to claim 17.
Furthermore, Luo 564 disclose wherein each entry of the plurality of entries in the programming adjustment data structure is identified by satisfying the temperature criterion and the PEC criterion [see Fig. 8: step 806, 810 and 814, one of operations 808, 812, and 816 is performed by the memory controller 115 to select one of the memory trim sets #1-#9, based on the temperature range and the P/E cycle range that are detected using the identified temperature and P/E cycle metrics, para. 86].
Regarding claim 19, Luo 564 in combination with Luo 555 and Liang et al. teach the limitation with respect to claim 18.
Furthermore, Luo 564 disclose wherein the temperature criterion is satisfied if the temperature falls within a temperature threshold range associated with a respective entry [the temperature management module 160 is configured to maintain a temperature metric 162, which is indicative of temperature applicable to at least a monitored region of the memory device 110. In an example, the temperature metric 162 includes two or more status bits that indicate a temperature range for the region of the memory device. The temperature range can be one of a predetermined number (e.g., two or more) of temperature ranges, with each temperature range having a corresponding temperature metric with which it is associated, para. 39].
Regarding claim 20, Luo 564 in combination with Luo 555 and Liang et al. teach the limitation with respect to claim 18.
Furthermore, Luo 564 disclose wherein the PEC criterion is satisfied if the number of PECs falls within a PEC threshold range associated with a respective entry [the P/E cycle management module 170 is configured to maintain a P/E cycle metric 172, which is indicative of a number of program-erase cycles performed by the memory device 110 within a selected time interval. In an example, the P/E cycle metric 172 includes two or more status bits that indicate a P/E cycle range for the number of P/E cycles performed by the memory device within the selected time interval. The P/E cycle range can be one of a predetermined number (e.g., two or more) of P/E cycle ranges, with each P/E cycle range having a corresponding P/E cycle metric with which it is associated, para. 42].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached at (571)272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DUY H LUONG/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825