DETAILED ACTION
This application, 18/424150, attorney docket GFSG2022056-US-NP, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application is assigned to Global Foundries Singapore Pte. Ltd., and has an effective filing date of 3/1/2023 based on the application date Applicant's election without traverse of Group I, claims 1-18 in the reply filed on 5/16/2025 is acknowledged. Claims 19-20 are withdrawn from further consideration. Claims 1-18 are pending and are considered below. Note that examiner will use numbers in parentheses to indicate numbered elements in prior art figures, and brackets to point to paragraph numbers where quoted material or specific teachings can be found.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claim 4 is rejected under 35 U.S.C. 112(a) o because the specification, while being enabling for a capacitor that uses the inductor winding as a first parallel plate, does not reasonably provide enablement for a capacitor that “does not include a first parallel plate arranged in parallel to the first plate” The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make the invention commensurate in scope with these claims. Both the specification and the claims improperly limit the capacitor to one without a second parallel plate. One skilled, a semiconductor device engineer would not understand how to build a one-plate capacitor.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 6, 9-14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Shimoichi. (U.S. 2020/0395353).
As for claim 1,
Shimoichi teaches a semiconductor device comprising:
a first layer (14) comprising a first inductor (L1, 41) and a second inductor (L2, 42), wherein a first path of the first inductor alternates with a second path of the second inductor (the spiral in opposing directions); and
a second layer (13) comprising a first capacitor (C2) comprising a first plate (32) and a second capacitor (c4) comprising a second plate (34), wherein the first plate is coupled in parallel with at least one of the first inductor or the second inductor and the second plate is coupled in parallel with at least one of the first inductor or the second inductor. (shown in figure 1 with common nodes with L1, so are connected electrically in parallel with the inductor)
Examiner notes that Shimoichi does not teach a choke device, the device is described as an LC circuit and its use as a choke is an intended use that does not limit the device. It has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F.2d 1647 (1987).
As for claim 6,
Shimoichi makes obvious the semiconductor device of claim 1, and teaches in figure 1 the first plate couples to a first terminal of the first inductor, and wherein the second plate couples to a second terminal of the second inductor. (Connections are at node 7).
As for claim 9,
Shimoichi makes obvious the semiconductor device of claim 6, and teaches a first protrusion (vias 162, figure 5) of the first plate couples to the first path of the first inductor (at 172), and wherein a second protrusion of the second plate couples to the second path of the second inductor. (via 163)
As for claim 10,
Shimoichi makes obvious the semiconductor device of claim 6, wherein the first plate is coupled from the first terminal to a third terminal (2) of the first inductor and the second plate is coupled from the second terminal to a fourth terminal (3) of the second inductor.
As for claim 11,
Shimoichi makes obvious the semiconductor device of claim 1, the semiconductor device further comprising:
a third layer (above 14c) comprising a first trace (218 at 2) and a second trace (218 at 3), wherein the first trace is coupled to at least one of the first inductor or the first plate and the second trace is coupled to at least one of the second inductor or the second plate. (shown in figure 5)
As for claim 12,
Shimoichi makes obvious the semiconductor device of claim 11, but does not teach that the first trace is configured to transmit a first High-Definition Multimedia Interface (HDMI) signal, and wherein the second trace is configured to transmit a second HDMI signal,
However, the transmitted signal is an intended use that does not limit the device. It has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F.2d 1647 (1987).
As for claim 13,
Shimoichi makes obvious the semiconductor device of claim 1, but does not teach the choke is configured to filter signals at at least one of 2.4 Gigahertz (GHz) or 5 GHz.
However, signal frequency is an intended use that does not limit the device. It has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F.2d 1647 (1987).
As for claim 14,
Shimiochi makes obvious in figures 1, 2 and 5, a substrate (12) comprising:
a first layer (14) comprising a first inductor (41) and a second inductor (42), wherein the first inductor alternates with the second inductor (The wind in alternating directions);
a second layer (13) comprising a first capacitor (C2) comprising a first plate (32); and at least one of the second layer or a third layer comprising a second capacitor (c4) comprising a second plate (34),
wherein the first plate is coupled to the first inductor (at 7) and the second plate is coupled to the second inductor (at 7).
As for claim 16,
Shimiochi makes obvious the substrate of claim 14, and teaches the first plate is coupled from a first terminal (7) to a third terminal (2) of the first inductor and the second plate is coupled from a second terminal (also 7) to a fourth terminal (4) of the second inductor.
Claims 2, 3 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Shimoichi in view of Montoriol (U.S. 8,736,034).
As for claim 2,
Shimoichi makes obvious the semiconductor device of claim 1, Shimoichi does not teach that the semiconductor device comprises a printed circuit board, and wherein the printed circuit board comprises the choke.
However, Montoriol teaches integrating the choke device of claim 1 into a PCB. ([co4 ln 60])
It would have been obvious to one skilled in the art at the effective filing date of this application to integrating the choke device of claim 1 into a PCB because it is it allows the IC to be connected to a larger device that may include an antenna, filters or matching circuits. Montoriol [co1 ln44]. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 3,
Shimoichi makes obvious the semiconductor device of claim 1, but does not teach the semiconductor device comprises a multi-chip module, and wherein the multi-chip module comprises the choke.
However, Montoriol teaches the choke device of claim 1 into a multi-chip module.
It would have been obvious to one skilled in the art at the effective filing date of this application to integrating the choke device of claim 1 into a multi-chip module because it is it allows the IC to be connected to a larger device that may include an antenna, filters or matching circuits. Montoriol [co1 ln44]. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 15,
Shimiochi makes obvious the substrate of claim 14, but does not teach that the substrate is formed as part of a printed circuit board or a multi-chip module.
However, Montoriol teaches integrating the device of claim 1 into a PCB. ([co4 ln 60]).
It would have been obvious to one skilled in the art at the effective filing date of this application to integrating the device of claim 1 into a PCB because it is it allows the IC to be connected to a larger device that may include an antenna, filters or matching circuits. Montoriol [co1 ln44]. One skilled in the art would have combined these elements with a reasonable expectation of success.
Claims 5, 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Shimoichi in view of Shekhar (U.S. 2021/03989444).
As for claim 5,
Shimoichi makes obvious the semiconductor device of claim 1, but does not teach that the first path comprises two or more first coils and the second path comprises two or more second coils, and wherein at least one coil of the two or more first coils alternates with a corresponding coil of the two or more second coils.
However, Shekhar teaches in figure 2B a first path comprises two or more first coils (243/244) and the second path comprises two or more second coils, and wherein at least one coil of the two or more first coils alternates with a corresponding coil of the two or more second coils. (cross section would alternate across the coils)
It would have been obvious to one skilled in the art at the effective filing date of this application use the interwoven coil traces as taught by Shekhar in the device of Shimoichi because it improves the coupling between the inductors. Shekhar [0033]. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 17,
Shimiochi makes obvious the substrate of claim 14,but does not teach that the first layer further comprises a third inductor and a fourth inductor, wherein the third inductor alternates with the fourth inductor and is spaced apart from the first inductor and the second inductor, the second layer further comprises a third capacitor comprising a third plate; and at least of the second layer or the third layer comprises a fourth capacitor comprising a fourth plate, and wherein the third plate is coupled to the third inductor and the fourth plate is coupled to the fourth inductor.
However, Shekhar teaches in figure 2B a first path comprises two or more first coils (243/244) and the second path comprises two or more second coils, and wherein at least one coil of the two or more first coils alternates with a corresponding coil of the two or more second coils. (Claim 17 requires remapping the inductor 42 to be the third inductor the interwoven coils cross section would alternate across the coils)
It would have been obvious to one skilled in the art at the effective filing date of this application use the interwoven coil traces as taught by Shekhar in the device of Shimoichi because it improves the coupling between the inductors. Shekhar [0033]. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 18,
Shimiochi makes obvious the substrate of claim 17, but does not teach that the first inductor, the second inductor, the first capacitor, and the second capacitor form a first choke configured to filter a first frequency, and wherein the third inductor, the fourth inductor, the third capacitor, and the fourth capacitor form a second choke configured to filter a second frequency.
However, both filter and frequency are intended uses of the device that do not distinguish the claimed device from the art of record. It has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F.2d 1647 (1987).
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 4 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(a) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As for claim 4, the prior art does not teach or make obvious the device of claim 1 that further includes first and second capacitors that do not include second parallel plates. Paragraph [0056] of the applicant’s disclosure describes that the inductor conductor functions as the second plate, so there is a plate, but it is common to the inductor and the capacitor, which is an unexamined limitation.
Claims 7 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As for claim 7,
Shimoichi teaches the semiconductor device of claim 6, but the prior art does not teach or make obvious the first plate couples to the first path of the first inductor and the second path of the second inductor, and wherein the second plate couples to the first path of the first inductor and the second path of the second inductor.
Claim 8 depends from claim 7 and includes the same novel limitation.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Liu et al (U.S. 2019/0200454) teaches an inductor/capacitor device that has a capacitor that uses the inductor as a plate of the capacitor, but the inductors are in different layers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN A BODNAR whose telephone number is (571)272-4660. The examiner can normally be reached M-Th and every other Friday 7:30-5:30 Central time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JOHN A BODNAR/Primary Examiner, Art Unit 2893
Prosecution Insights