DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 8, 9, 10, 17, 18 are rejected under 35 U.S.C. 102(a)(b) as being anticipated by
Xiang (CN 105808486 A)
Regarding claim 1: Xiang, Fig. 1, discloses a predriver (Abstract ) comprising: a voltage reference node (VBN); a set of branches (predriver transistor branches) coupled to the voltage reference node (VBN), wherein each branch comprises a set of n-type metal-oxide semiconductor (NMOS) transistors (Fig.1); an active inductor (Abstract ) coupled to the voltage reference node (VBN); and an amplifier (Main driver, differential amplifier structure) (Abstract ), wherein an input (VIN/VIP differential input nodes) of the amplifier is coupled to the voltage reference node (through the NMOS structures biased by VBN), and an output (VOP/VON) of the amplifier is coupled to a predriver output (VOP/VON).
Regarding claim 8: Xiang discloses the active inductor (Fig.2) comprises:
a capacitor (CZ) and a resistor (RZ) coupled in series between a first voltage source (upper supply rail ) and the voltage reference node (VBN-controlled node/active-inductor node); and a p-type metal-oxide semiconductor (PMOS) transistor (MP) coupled between the first voltage source (upper supply rail) and the voltage reference node (active-inductor output/load node), the PMOS transistor (MP) comprising a gate (gate of MP) coupled to a node between the capacitor (CZ) and the resistor (RZ).
Regarding claim 9: Xiang, discloses (Fig. 3) comprises an impedance matching component (“MP and RS is the signal path load, to achieve impedance matching”) (Abstract) coupled to the output of the amplifier (OutN/OutP).
Regarding claim 10: Xiang, Fig.1, Fig. 3, disclose a system comprising: a driver (Main Driver)(Fig. 1); and a predriver (predriver1 and/or predriver2) (Fig.1, abstract) coupled to the driver (Main Driver)(Fig.1), wherein the predriver (predriver1, predriver2) comprises: a voltage reference node (VBN)(Fig.1); a set of branches (predriver transistor branches) (Fig. 1) coupled to the voltage reference node (VBN), wherein each branch comprises a set of n-type metal-oxide semiconductor (NMOS) transistors (receiving VBN and coupled to ground) (Fig. 1); an active inductor (Main Driver) (Fig.1) coupled to the voltage reference node (VBN); and an amplifier (Mdiff, differential amplifier structure) (Fig.3), wherein an input (differential inputs VIP/VIN) of the amplifier (Mdiff, differential amplifier structure)(Fig.3) is coupled to the voltage reference node (through a VBN1-controlled transistor branch), and an output (OutN/OutP)(Fig.3) of the amplifier (Mdiff, differential amplifier structure) (Fig.3) is coupled to an input (Vin/Vip)(Fig.3) of the driver (Main Driver)(Fig.1).
Regarding claim 17: Xiang, Fig. 2, discloses the active inductor comprises: a capacitor (CZ) and a resistor (RZ) coupled in series between a first voltage source (upper supply rail) and the voltage reference node (VBN-controlled node/active-inductor node); and a p-type metal-oxide semiconductor (PMOS) transistor (MP) coupled between the first voltage source (upper supply rail) and the voltage reference node (active-inductor output/load node), the PMOS transistor (MP) comprising a gate (gate of MP) coupled to a node (MP gate-control node) between the capacitor (CZ) and the resistor (RZ).
Regarding claim 18: Xiang, Fig. 3, discloses, wherein the output of the amplifier (OutN/OutP) is coupled to the input of the driver by an impedance matching component (“MP and RS is the signal path load, to achieve impedance matching”)(Abstract).
Allowable Subject Matter
Claims 2 – 7, 11- 16, 19, 20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Regarding claim 2, none of the references teaches the claimed branch architecture in which the set of NMOS transistors of a first branch of the set of branches comprises: a first NMOS transistor coupled to a first selector line; a second NMOS transistor coupled to a second selector line; and a third NMOS transistor coupled to a first data line, wherein the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are coupled in series between the voltage reference node and a ground node as a first series
Regarding claim 11, none of the references teaches the corresponding system including the claimed branch architecture in which the set of NMOS transistors of a first branch of the set of branches comprises: a first NMOS transistor coupled to a first selector line; a second NMOS transistor coupled to a second selector line; and a third NMOS transistor coupled to a first data line, wherein the first NMOS transistor, the second NMOS transistor and the third NMOS transistor are coupled in series between the voltage reference node and a ground node as a first series.
Regarding claim 19, none of the references teaches the corresponding method of operating the claimed branch architecture including receiving respective clock and data signals at NMOS transistors of multiple branches coupled to the voltage reference node, adjusting a signal using the active inductor, amplifying the adjusted signal, and outputting the amplified signal as recited.
Claims 3-7, 12-16, and 20 depend therefrom and include the same allowable features.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Stoerk (US 2020/0204171 A1) and Lee et al. (US 2009/0279360 A1), disclose various NMOS transistor architectures, branch arrangements, and control circuitry associated with semiconductor devices. Stoerk teaches explicit NMOS transistor structures, multiple transistor branches, current mirror legs, bias circuitry, and associated control circuitry. Lee teaches repeated NMOS transistor chains, serially connected NMOS devices, and distinct word lines, bit lines, and source lines within a memory array architecture.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATASHA Y MARANO whose telephone number is (571)272-9512. The examiner can normally be reached Mon - Fri 7:30am - 3:30pm.
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/Jessica Han/
Supervisory Patent Examiner, Art Unit 2843
/NATASHA Y. MARANO/
Examiner
Art Unit 2843
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