Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II in the reply filed on 05/13/2026 is acknowledged.
Claims 1-8 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 05/13/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 9-12 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Hu et. Al. (US 20230025541 A1 hereinafter Hu).
Regarding claim 9, Hu teaches in Figs. 1A-1C with associated text a stack type semiconductor device comprising:
a first semiconductor structure (lowest chip 102) having a first surface (upper surface S2) and a
second surface (lower surface S1) opposite to the first surface, the first semiconductor
structure including at least one memory component 106 on the first surface [0039]
and a logic circuit layer 150 on the second surface (Fig. 1A, [0054]); and
a second semiconductor structure (102 over the first semiconductor structure) having a third surface S1 and a fourth surface S2 opposite to the third surface, the second semiconductor
structure including a control circuit layer 104 integrated on the third surface to control the at least one memory component (Fig. 1C, [0050]),
wherein the first semiconductor structure and the second semiconductor structure are hybrid-bonded to face the at least one memory component and the control circuit layer (Fig. 1C, [0050]).
Regarding claim 10, Hu teaches the at least one memory component comprises a plurality of capacitors 106 (Fig. 1C, [0047]),
and the control circuit layer comprises a plurality of access transistors
configured to selectively transmit data to the plurality of capacitors (Fig. 1C, [0050]).
Regarding claim 11, Hu teaches the first semiconductor structure further comprises a first bonding layer (146, 142 and 144) positioned on the at least one memory component and hybrid-bonded to the second semiconductor structure (Fig. 1C, [0051]), and
wherein the first bonding layer comprises: a plurality of first bonding pads 142 electrically connected to the at least one memory component (Fig. 1C, [0049]); and
a first bonding insulation layer 146 configured to electrically isolate the plurality of first bonding pads from each other (Fig. 1C, [0049]).
Regarding claim 12, Hu teaches the second semiconductor structure further comprises a second bonding layer (130 and 126) positioned on the control circuit layer (Fig. 1C, [0046]), and
wherein the second bonding layer comprises: a plurality of second bonding pads 126 electrically connected to the control circuit layer and bonded to the plurality of first bonding pads (Fig. 1C, [0051]);
and
a second bonding insulation layer 130 configured to electrically isolate the plurality of second bonding pads from each other (Fig. 1C, [0046]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Hu as applied to claim 9 and further in view of Yokoyama et. Al. (US 20190363129 A1 hereinafter Yokoyama).
Regarding claim 13, Hu teaches in Fig. 1 with associated text a the stack type semiconductor device of claim 10.
Hu does not specify the logic circuit layer comprises at least one of an arithmetic and logic circuit for calculating data in the at least one memory component, a data pipeline circuit, an interface circuit for receiving and processing an external signal, and at least one analog element.
Yokoyama teaches in Fig. 1 with associated text a logic circuit layer 200 similar to that of Hu wherein the logic circuit layer comprises at least one of an arithmetic and logic circuit for calculating data in the at least one memory component, a data pipeline circuit, an interface circuit for receiving and processing an external signal, and at least one analog element (analog circuit [0100]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use at least one of an arithmetic and logic circuit for calculating data in the at least one memory component, a data pipeline circuit, an interface circuit for receiving and processing an external signal, and at least one analog element in the logic circuit of Hu as taught by Yokoyama because according to Yokoyama a logic circuit block and an analog circuit that configure a functional circuit are typically mounted as the other circuits 220 in addition to the peripheral circuit 210 [0100].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON J GRAY whose telephone number is (571)270-7629. The examiner can normally be reached Monday-Friday 9am-4pm.
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/AARON J GRAY/Examiner, Art Unit 2897
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