DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II in the reply filed on 7/13/2026 is acknowledged.
Claims 1-9 are canceled from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/13/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 10-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Luo et al (US 2022/0406719; hereinafter Luo).
Regarding claim 10, Fig 1K and 2 of Luo discloses a memory device comprising:
a stack structure (152/104; Fig 1K) comprising tiers each comprising a conductive structure (156; Fig 1K; ¶ [0068]) and an insulative structure (104; Fig 1K; ¶ [0068]) vertically neighboring the conductive structure;
staircase structures (105; Fig 1K; ¶ [0032]) comprising steps comprising horizontal edges of the tiers, the steps individually defined by more than one of the tiers (Fig 1K);
a first conductive contact structure (182; Fig 1K; ¶ [0088]) in contact with a vertically uppermost conductive structure (156; Fig 1K; ¶ [0068]) of one of the steps;
a second conductive contact structure (180; Fig 1K; ¶ [0088]) in contact with a vertically uppermost conductive structure (156; Fig 1K; ¶ [0068]) of the one of the steps, the second conductive structure (180; Fig 1K; ¶ [0088]) farther from a horizontal center of the one of the steps in a first horizontal direction than the first conductive contact structure (182; Fig 1K; ¶ [0088]); and
strings of memory cells (165; Fig 1K; ¶ [0077]) vertically extending through portions of the stack structure (152/104; Fig 1K) neighboring the staircase structures in a second horizontal direction.
Regarding claim 11, Fig 1K and 2 of Luo discloses pillar structures (150; Fig 1K; ¶ [0056]) vertically extending through the stack structure at the horizontal edges of the tiers. (Fig 1K)
Regarding claim 12, Fig 1K and 2 of Luo discloses a first portion of each of the pillar structures (150; Fig 1K; ¶ [0056]) is located outside of horizontal boundaries of the steps in the second horizontal direction and a second portion of the pillar structures are located within horizontal boundaries of the steps in the second horizontal direction. (Fig 1K)
Regarding claim 13, Fig 1K and 2 of Luo discloses a slot structure (160; Fig 1H; 2; ¶ [0069]) horizontally extending through the memory device in second first horizontal direction and separating the memory device into block structures (162; Fig 1H; ¶ [0070]) each individually comprising some of the staircase structure.
Regarding claim 14, Fig 1K and 2 of Luo discloses the first conductive contact structure (182; Fig 1K; ¶ [0088]) is located closer (Fig 1H) to the slot structure (160; Fig 1H; 2; ¶ [0069]) than the second conductive contact structure. (Figs 1H-1K, 2)
Regarding claim 15, Fig 1K and 2 of Luo discloses the first conductive contact structure (182; Fig 1K; ¶ [0088]) and the second conductive contact structure (180; Fig 1K; ¶ [0088]) individually comprise a contact connection region (Fig 1K, 2) vertically between the one of the steps and a vertically uppermost surface of the stack structure (Fig 2).
Regarding claim 16, Fig 1K and 2 of Luo discloses the first conductive contact structure (182; Fig 1K; ¶ [0088]) and the second conductive contact structure (180; Fig 1K; ¶ [0088]) individually horizontally extend in the first horizontal direction within the contact connection region (Figs 1K, 2).
Regarding claim 17, Fig 1K and 2-3 of Luo discloses an electronic system (Fig 3) comprising:
an input device (Fig 3);
an output device (Fig 3);
a processor device (Fig 3) operably coupled to the input device and the output device; and
a memory device (Fig 3) operably coupled to the processor device (Fig 3) and comprising at least one microelectronic device, the at least one microelectronic device comprising:
a stack structure (152/104; Fig 1K) comprising tiers each comprising a conductive structure (156; Fig 1K; ¶ [0068]) and an insulative structure (104; Fig 1K; ¶ [0068]) vertically neighboring the conductive structure;
staircase structures (105; Fig 1K; ¶ [0032]) comprising steps comprising horizontal edges of the tiers, the steps individually defined by more than one of the tiers (Fig 1K);
a first conductive contact structure (182; Fig 1K; ¶ [0088]) in contact with a vertically uppermost conductive structure (156; Fig 1K; ¶ [0068]) of one of the steps;
a second conductive contact structure (180; Fig 1K; ¶ [0088]) in contact with a vertically uppermost conductive structure (156; Fig 1K; ¶ [0068]) of the one of the steps, the second conductive structure (180; Fig 1K; ¶ [0088]) farther from a horizontal center of the one of the steps in a first horizontal direction than the first conductive contact structure (182; Fig 1K; ¶ [0088]); and
strings of memory cells (165; Fig 1K; ¶ [0077]) vertically extending through portions of the stack structure (152/104; Fig 1K) neighboring the staircase structures in a second horizontal direction.
Regarding claim 18, Fig 1K and 2-3 of Luo discloses the each of the steps are defined by horizontal edges of three of the tiers (Fig 1K).
Regarding claim 19, Fig 1K and 2-3 of Luo discloses the conductive contact structures (182; Fig 1K; ¶ [0088]) in contact with portions of vertically uppermost conductive structures defining the steps are located farther from a center of the staircase structure (Fig 1K) than the conductive contact structures in contact with vertically lowermost conductive structures defining the steps (Fig 1K).
Regarding claim 20, Fig 1K and 2-3 of Luo discloses each conductive level of each steps is individually in contact with two of the conductive contact structures (Fig 1K).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Lee et al (US 2017/0256551)
Park (US 10396035)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RATISHA MEHTA whose telephone number is (571)270-7473. The examiner can normally be reached Monday-Friday: 9:00am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos Feliciano can be reached at 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RATISHA MEHTA/Primary Examiner, Art Unit 2817
Prosecution Insights