DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 13-20 in the reply filed on 6/16/26 is acknowledged.
Claims 1-12 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/16/26.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 10/01/24. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 13-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yeh et al. (US PGPub 2020/0098774, hereinafter referred to as “Yeh”).
Yeh discloses the semiconductor device as claimed. See figures 1-23 and corresponding texted, where Yeh teaches, in claim 13, a microelectronic device, comprising:
a stack structure (N planes) comprising tiers each including conductive material (WL) vertically neighboring insulative material (311, 312, 313, 314, 315), the stack structure divided into blocks horizontally extending in parallel in a first direction and separated from one another in a second direction orthogonal to the first direction by insulative slot structures, at least one of the blocks comprising:
a slot (1461) vertically extending through all of the tiers and comprising:
a first region horizontally extending in the first direction (figures 14 and 14A; [0102]); and
second regions intersecting the first region and horizontally extending in at least one third direction angled relative to the first direction and the second direction (figures 14 and 14A; [0102-0107]); and
memory string structures (600) vertically extending through the stack structure and within horizontal areas of the second regions of the slot, the memory string structures horizontally separated from one another in the at least one third direction (figures 6-6B; [0086-0090]).
Yeh teaches, in claim 14, wherein the memory string structures each comprise: (figures 3A and 3B; [0067-0071])
a volume of a first dielectric oxide material on a sidewall of the stack structure partially defining the slot ([0071]);
a volume of a dielectric nitride material on the volume of the first dielectric oxide material ([0071]);
a volume of a second dielectric oxide material on the volume of the dielectric nitride material ([0071]); and
a volume of semiconductor material on the volume of the second dielectric oxide material.
Yeh teaches, in claim 15, further comprising a base structure vertically underlying the stack structure and comprising:
source contact structures (128) within the horizontal areas of the second regions of the slot of the at least one of the blocks and contacting the memory string structures of the at least one of the blocks; and
additional conductive material (129) contacting side surfaces of the source contact structures (128) (figure 1; [0049-0066]).
Yeh teaches, in claim 16, wherein the source contact structures individually comprise: (figure 1; [0049-0066])
an additional volume of the first dielectric oxide material;
an additional volume of the dielectric nitride material on the additional volume of the first dielectric oxide material (figures 3A and 3B; [0067-0071]);
an additional volume of the second dielectric oxide material on the additional volume of the dielectric nitride material (figures 3A and 3B; [0071]); and
an additional volume of the semiconductor material (370) on the additional volume of the second dielectric oxide material, the additional volume of the semiconductor material continuous with the volume of the semiconductor material of each of the memory string structures (figures 3A and 3B; [0071-0072]).
Yeh teaches, in claim 17, wherein the additional conductive material of the base structure (IG) ([0020]) directly physically contacts the additional volume of the semiconductor material of each of the source contact structures (figures 3A and 3B; [0067-0072]).
Yeh teaches, in claim 18, wherein each of the source contact structures horizontally overlaps and contacts multiple of the memory string structures (figures 3A and 3B; [0067-0072]).
Yeh teaches, in claim 19, further comprising drain contact structures within the horizontal areas of the second regions of the slot and contacting the memory string structures, the drain contact structures vertically overlying and horizontally overlapping the source contact structures (figures 3A and 3B; [0067-0072]).
Yeh teaches, in claim 20, a memory device, comprising:
a stack structure (N planes) comprising:
blocks extending in parallel in a first horizontal direction and individually including tiers each comprising conductive material (WL) and insulative material (311, 312, 313, 314, 315) vertically neighboring the conductive material, the blocks individually comprising:
an at least partially filled slot vertically extending through the tiers and comprising:
a backbone region (161) substantially linearly extending in the first horizontal direction; and
rib regions (141-143) intersecting the backbone region and individually substantially linearly extending in at least one second horizontal direction angled relative to the first horizontal direction; vertically extending strings of memory cells within horizontal areas of the rib regions of the at least partially filled slot; and
a base structure vertically below the stack structure and comprising:
source contact structures (128) in electrical communication with the vertically extending strings of memory cells (600); and
laterally extending conductive structures contacting sidewalls of the source contact structures (128) (figure 1; [0049-0066]).
Conclusion
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/STANETTA D ISAAC/Examiner, Art Unit 2898 July 11, 2026
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