CTNF 18/424,713 CTNF 89623 DETAILED ACTION This office action is in response to the election of claims filed on May 22, 2026. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Acknowledgements Applicant's election without traverse of Invention II (Claims 11-20) in the reply filed on May 22, 2026, is acknowledged. The present office action is made with all the suggested amendments being fully considered. Accordingly, claims 1-20 are currently pending in this application. Claims 1-10 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Information Disclosure Statement The information disclosure statements (IDS) submitted on 1/26/2024 and 7/8/2024 are being considered by the examiner. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 18-20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Parekh (US 2022/0246681) . With respect to Claim 18 , Parekh discloses (Fig. 1F) all aspects of the current invention including a memory device (224), comprising: a stack structure (114) comprising tiers each comprising conductive material (140) and insulative material (142) vertically neighboring the conductive material; strings of memory cells (146) vertically extending through the stack structure a source structure (120/136) vertically underlying the stack structure and coupled to the strings of memory cells digit line (122) vertically overlying the stack structure and coupled to the strings of memory cells a semiconductor structure (190/212/168) vertically overlying the digit lines capacitors (196) partially vertically overlapping lowermost boundaries of the semiconductor structure control logic devices (168/170) partially vertically overlapping uppermost boundaries of semiconductor structure and coupled to the strings of memory cells conductive contact structures (191,172) vertically extending through the semiconductor structure and coupling at least some the capacitors to some of the control logic devices With respect to Claim 19 , Parekh discloses (Fig. 1F) further comprising conductive routing structures (174) vertically overlying the control logic devices, one or more of the conductive routing structures (left 174) coupled to one or more of the control logic devices, and one or more other of the conductive routing structures (right 174) coupled to the source structure. With respect to Claim 20 , Parekh discloses (Fig. 1F) further comprising additional conductive contact structures (116) coupling the source structure to the one or more other of the conductive routing structures, at least some of the additional conductive contact structures horizontally overlapping one another and vertically extending between the source structure and the one or more other of the conductive routing structures . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 11-14, 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Parekh (US 2022/0246681) in view of Fastow (US 2019/0043836) With respect to Claim 11 , Parekh discloses (Fig. 1F) most aspects of the current invention including a microelectronic device, comprising: a stack structure (114) comprising tiers each comprising conductive material (140) and insulative material (142) vertically neighboring the conductive material; cell pillar structures (118) comprising semiconductor materiel vertically extending through the stack structure; a semiconductor structure (190/212/168) vertically overlying the stack structure; first devices (190/196) at a lower boundary of the semiconductor structure; second devices (168/170) at an upper boundary of the semiconductor structure; Furthermore, although Parekh discloses conductive contact structures vertically extending the through the semiconductor structure, Parekh fails to disclose conductive contact structures vertically extending from a vertical position of at least some of the second devices, completely through the semiconductor structure, and at least to an additional vertical position of at least some of the first devices. On the other hand, and in the same field of endeavor, Fastow teaches (Fig 2A) a microelectronic device, comprising a stack structure (281b) comprising tiers each comprising conductive material and insulative material vertically neighboring the conductive material, a semiconductor structure (282a/282b) vertically overlying the stack structure, first devices (transistors in 284b) at a lower boundary of the semiconductor structure, second devices (transistors in 284a) at an upper boundary of the semiconductor structure and conductive contact structures (vias 286a, 28b) vertically extending from a vertical position of at least some of the second devices, completely through the semiconductor structure, and at least to an additional vertical position of at least some of the first devices. Fastow teaches the conductive contact structures are formed through the CMOS circuitry and substrates to couple the CMOS circuitry and further helps to improve routing and increase signal density (par 38). Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to incorporate conductive contact structures vertically extending from a vertical position of at least some of the second devices, completely through the semiconductor structure, and at least to an additional vertical position of at least some of the first devices in the device of Parekh because the conductive contact structures are formed through the CMOS circuitry and substrates to couple the CMOS circuitry and further helps to improve routing and increase signal density. With respect to Claim 12 , Parekh discloses (Fig. 1F) wherein the first devices (190/196) comprise one or more of metal-insulator-semiconductor (MIS) capacitors and metal-insulator- metal (MIM) capacitors (par 83,85) With respect to Claim 13 , Parekh discloses (Fig. 1F) wherein the second devices (168/170) comprise control logic devices including transistors partially vertically overlapping the semiconductor structure (par 62-63) With respect to Claim 14 , Parekh discloses (Fig. 1F) further comprising: a source structure (120/136) vertically underlying the stack structure and coupled to the cell pillar structures; and digit line structures (122) vertically interposed between the first devices and the stack structure and coupled to the cell pillar structures; and additional contact structures (116) horizontally offset from the cell pillar structures and individually vertically extending completely through the stack structure and to the source structure. With respect to Claim 16 , Parekh discloses (Fig. 1F) further comprising: conductive routing structures (214) vertically overlying the second devices; and conductive pad structures (218) vertically overlying and coupled to at least some of the conductive routing structures With respect to Claim 17 , Parekh discloses (Fig. 1F) further comprising additional conductive contact structures (220) coupled to some of the conductive routing structures and continuously vertically extending from positions vertically overlying at least some of the second devices to the stack structure . 07-21-aia AIA Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Parekh (US 2022/0246681) in view of Fastow (US 2019/0043836) and in further view of Kim (US 2023/0403866) . With respect to Claim 15 , Parekh in view of Fastow disclose most aspects of the present invention. Furthermore, Parekh discloses (Fig. 1F) further comprising: digit line contact structures (126) vertically interposed between the first devices and the digit line structures and coupled to the digit line structures. However, the combination of references do not show conductive bond pad structures vertically interposed between the first devices and the digit line contact structures coupled to the digit line contact structures. On the other hand, and in the same field of endeavor, Kim teaches (Fig 1) a microelectronic device (100), comprising a stack structure comprising tiers each comprising conductive material (130) and insulative material (120) vertically neighboring the conductive material, a semiconductor structure (S2) vertically overlying the stack structure, first devices (220) at a lower boundary of the semiconductor structure, a source structure (104/102) vertically underlying the stack structure and coupled to cell pillar structures; and digit line structures (182) vertically interposed between the first devices and the stack structure and coupled to the cell pillar structures, and further comprising digit line contact structures (184) vertically interposed between the first devices and the digit line structures and coupled to the digit line structures, and conductive bond pad structures (198/298) vertically interposed between the first devices and the digit line contact structures coupled to the digit line contact structures. Kim teaches the conductive bond pad structures allow the first substrate structure to be electrically and physically connected to the second substrate structure (par 44). Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to incorporate conductive bond pad structures vertically interposed between the first devices and the digit line contact structures coupled to the digit line contact structures, in the device of Parekh and Fastow, because the conductive bond pad structures allow the first substrate structure to be electrically and physically connected to the second substrate structure. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUINTON A BRASFIELD whose telephone number is (571)272-0804. The examiner can normally be reached M-F 9AM-4PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Q.A.B/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814 Application/Control Number: 18/424,713 (Non-Final Rejection) Page 2 Art Unit: 2814 Application/Control Number: 18/424,713 (Non-Final Rejection) Page 4 Art Unit: 2814 Application/Control Number: 18/424,713 (Non-Final Rejection) Page 5 Art Unit: 2814 Application/Control Number: 18/424,713 (Non-Final Rejection) Page 6 Art Unit: 2814 Application/Control Number: 18/424,713 (Non-Final Rejection) Page 7 Art Unit: 2814 Application/Control Number: 18/424,713 (Non-Final Rejection) Page 9 Art Unit: 2814 Application/Control Number: 18/424,713 (Non-Final Rejection) Page 10 Art Unit: 2814
Prosecution Insights