DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 05/11/2026. Claims 1-20 are pending for this examination.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed on 03/16/2024.
Oath/Declaration
The oath or declaration filed on 01/29/2024 is acceptable.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/29/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Election/Restrictions
Applicant’s election, without traverse Species I, directed to an embodiment as depicted in FIGS. [2-4], with claims 1-10 and 13-20, in the “Response to Election / Restriction Filed” filed on 05/11/2026 is acknowledged and entered.
This office action considers claims 1-20 are thus pending for prosecution, of which, non-elected claims 11-12 are withdrawn, and elected claims 1-10 and 13-20 are examined on their merits.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-5 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding Claim 4, The instant claims recite limitation “wherein the voltage supply line and the upper guard line are located on substantially the same plane over the substrate” is not clear because substantially the same plane is not defined and it also has lack of antecedent issue. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate corrections defining these limitations within metes and bounds of the claimed invention are required.
Regarding Claim 5, The instant claims recite limitation “wherein the voltage supply line and the upper guard line include substantially the same material” is not clear because substantially the same material is not defined and it also has lack of antecedent issue. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate corrections defining these limitations within metes and bounds of the claimed invention are required.
Regarding Claim 15, The instant claims recite limitation “wherein the voltage supply line and the upper guard line are located on substantially the same plane over the substrate” is not clear because substantially the same plane is not defined and it also has lack of antecedent issue. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate corrections defining these limitations within metes and bounds of the claimed invention are required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6-7 and 14-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by LEE et al (US 2024/0194616 A1; hereafter LEE).
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Regarding claim 1. LEE discloses a semiconductor chip (Fig [2, 9], semiconductor device 100e) comprising:
a chip region (Fig [2, 9], main chip region MC, Para [ 0026]) and a chip sealing region (sealing region MS, Para [ 0026]) disposed in a substrate (substrate 110, Para [ 0024]);
a circuit pattern (PWS, Para [ 0036]) structure disposed in the chip region (main chip region MC, Para [ 0026]);
a chip guard structure (back ring structure BR1, Para [ 0048]) disposed in the chip sealing region (sealing region MS, Para [ 0026]) and surrounding the chip region (main chip region MC, Para [ 0026]);
a voltage supply line (power connection conductive layer PCL, Para [ 0036]) disposed over the circuit pattern structure (PWS, Para [ 0036]) in the chip region (main chip region MC, Para [ 0026]) and supplying a predetermined voltage (PWS, Para [ 0036]) to the circuit pattern structure (PWS, Para [ 0036]); and
an upper guard line (front ring structure FR1, Para [ 0039]) disposed over the chip guard structure (back ring structure BR1, Para [ 0048]) in the chip sealing region (sealing region MS, Para [ 0026]) and electrically connected to the voltage supply line (power connection conductive layer PCL, Para [ 0036]).
Regarding claim 2. LEE discloses the semiconductor chip of claim 1, LEE discloses wherein the upper guard line (front ring structure FR1, Para [ 0039]) is disposed to surround the chip region (main chip region MC).
Regarding claim 3. LEE discloses the semiconductor chip of claim 1, LEE discloses further comprising a conductive connection pattern (connection wire CL4, Para [ 0078]) connecting (electrically) the voltage supply line (power connection conductive layer PCL, Para [ 0036]) to the upper guard line (front ring structure FR1, Para [ 0039]).
Regarding claim 4. LEE discloses the semiconductor chip of claim 1, LEE discloses wherein the voltage supply line (power connection conductive layer PCL, Para [ 0036]) and the upper guard line are (front ring structure FR1, Para [ 0039]) located on substantially the same plane over the substrate (substrate 110, Para [ 0024]).
Regarding claim 6. LEE discloses the semiconductor chip of claim 1, LEE discloses wherein the chip guard structure (back ring structure BR1, Para [ 0048]) is disposed to surround the chip region (main chip region MC), and wherein the upper guard line (front ring structure FR1, Para [ 0039]) is disposed to overlap the chip guard structure (back ring structure BR1, Para [ 0048]) in a direction perpendicular or substantially perpendicular to a surface of the substrate (substrate 110, Para [ 0024]).
Regarding claim 7. LEE discloses the semiconductor chip of claim 1, LEE discloses wherein the upper guard line (front ring structure FR1, Para [ 0039]) is physically separated from the chip guard structure (back ring structure BR1, Para [ 0048]).
Regarding claim 14. LEE discloses a semiconductor chip comprising:
a substrate (substrate 110, Para [ 0024]) including a chip region (main chip region MC, Para [ 0026]) and a chip sealing region (sealing region MS, Para [ 0026]) located outside the chip region (main chip region MC, Para [ 0026]);
a chip guard structure (back ring structure BR1, Para [ 0048]) disposed in the chip sealing region (sealing region MS) to surround the chip region (main chip region MC, Para [ 0026]);
a voltage supply line (power connection conductive layer PCL, Para [ 0036]) disposed in the chip region (main chip region MC, Para [ 0026]); and
an upper guard line (front ring structure FR1, Para [ 0039]) disposed in the chip sealing region (sealing region MS, Para [ 0026]) spaced apart from the chip guard structure (back ring structure BR1, Para [ 0048]) over the substrate (substrate 110, Para [ 0024]), the upper guard line (front ring structure FR1, Para [ 0039]) electrically insulated from the chip guard structure (back ring structure BR1, Para [ 0048]), and electrically connected to the voltage supply line (power connection conductive layer PCL, Para [ 0036]).
Regarding claim 15. LEE discloses the semiconductor chip of claim 14, LEE discloses wherein the voltage supply line (power connection conductive layer PCL, Para [ 0036], Para [ 0036]) and the upper guard line (front ring structure FR1, Para [ 0039]) are located on substantially the same plane over the substrate (substrate 110, Para [ 0024]).
Regarding claim 16. LEE discloses the semiconductor chip of claim 15, LEE discloses further comprising a conductive connection pattern (connection wire CL4, Para [ 0078]) connecting the voltage supply line (power connection conductive layer PCL) to the upper guard line (front ring structure FR1, Para [ 0039]).
Regarding claim 17. LEE discloses the semiconductor chip of claim 14, LEE discloses further comprising a circuit pattern structure (PWS, Para [ 0036]) disposed in the chip region (main chip region MC) to receive a predetermined voltage from the voltage supply line (power connection conductive layer PCL, Para [ 0036]).
Regarding claim 18. LEE discloses the semiconductor chip of claim 14, LEE discloses wherein the upper guard line (front ring structure FR1, Para [ 0039]) is disposed to overlap the chip guard structure (back ring structure BR1, Para [ 0048]) in a direction perpendicular or substantially perpendicular to a surface of the substrate (substrate 110, Para [ 0024]).
Allowable Subject Matter
Claims 8-10, 13 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 8. The semiconductor chip of claim 1, wherein the voltage supply line includes: a power pad receiving the predetermined voltage from an external device; and a redistribution layer extending from the power pad.
Claim 9 is objected based on the dependency of claim 8.
Regarding claim 10. The semiconductor chip of claim 1, wherein the voltage supply line includes: a ground pad receiving a ground voltage from an external device; an operation voltage pad receiving an operation voltage from the external device; a first redistribution layer extending from the ground pad; and a second redistribution layer extending from the operation voltage pad.
Regarding claim 13. The semiconductor chip of claim 1, wherein the chip guard structure includes: at least two guard metal layers disposed over a surface of the substrate spaced apart from each other in a direction perpendicular or substantially perpendicular to the surface of the substrate; an intermetal contact layer connecting the at least two guard metal layers to each other; and a lower contact layer connecting a lowest guard metal layer among the at least two guard metal layers and a ground well of the substrate to each other.
Regarding claim 19. The semiconductor chip of claim 14, wherein the voltage supply line includes: a power pad receiving the predetermined voltage from an external device; and a redistribution layer extending from the power pad.
Claim 20 is objected based on the dependency of claim 19.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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