DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 01/29/2024 and 12/20/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the other side of the two gate structures " in the 9th line of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claims 2-15 are rejected because they depend on the rejected claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 and 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Reznicek et al. (US 20210159270 A1) in view of Yao (US 20240155850 A1).
Regarding claim 1, Reznicek et al. teach a semiconductor layout pattern (Figs. 1 and 14), comprising: a substrate (10; Figs. 1 and 14, [0041]) including a MRAM (magnetic random access memory) region (Figs. 1 and 14B; [0040]); wherein each MRAM cell (each memory cell having a MTJ pillar 32P; Fig. 4, [0076]) comprises: two fin structures (the top two 12s; Figs. 1 and 14, [0040]) parallel to each other and arranged along a X direction (the horizontal direction in Fig. 1A); two gate structures (the center and the right 16s; Figs. 1 and 14A, [0040]) parallel to each other and arranged along a Y direction (the vertical direction in Fig. 1A); a drain metal layer (the right source/drain contact structure 26 in Fig. 14A) located between the two gate structures (the center and the right 16s; see Fig. 14A); two source metal layers (56S and 66X; Fig. 14A, [0094, 0099]) located on the other side of the two gate structures (the left side of the center and the right 16s;, see Fig. 14A) relative to (close to) the drain metal layer (the right 26 in Figs. 1 and 14A); and an MTJ (magnetic tunneling junction) element (32P; Fig. 4, [0076]) electrically connected to the drain metal layer (the right 26; see Fig. 14A).
Reznicek et al. do not teach a semiconductor layout pattern including a high-voltage device, a substrate including a high-voltage device region and a MRAM region adjacent to each other; the MRAM region at least comprises a plurality of MRAM cells arranged in an array.
In the same field of endeavor of MRAM, Yao teaches a semiconductor layout pattern (Fig. 4, [0032]) including a high-voltage device (peripheral circuits 47 or 48 which can perform write/program operations in high voltages; Fig. 4, [0032, 0028, 0040]), a substrate (41; Fig. 4, [0032]) including a high-voltage device region (peripheral circuits 47 or 48 which can perform write/program operations in high voltages; Fig. 4, [0032, 0028, 0040]) and a MRAM region (44; Fig. 4, [0026]) adjacent to each other (see Fig. 4); the MRAM region (44) at least comprises a plurality of MRAM cells ([0026]) arranged in an array (a part of memory array 42; Fig. 4, [0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the inventions of Reznicek et al. and Yao, and to further include the peripheral circuits able to provide high voltages on the substrate of Reznicek et al. as taught by Yao, because the peripheral circuits of Yao can have an extra ability of providing high voltages to make a MRAM cell a one-time programmable memory cell as taught by Yao ([0032, 0028, 0040] of Yao).
Regarding claim 9, Reznicek et al. teach the semiconductor layout pattern according to claim 1, further comprising a bit line (66Y, can be used as bit line; Fig. 14A, [0098]) electrically connected to the drain metal layer (the right 26 in Figs. 1 and 14A; Figs. 1 and 14).
Regarding claim 10, Reznicek et al. teach the semiconductor layout pattern including a high-voltage device according to claim 1, wherein the MTJ element (32P) is located above the drain metal layer (the right 26 in Fig. 14A), and the MTJ element (32P) is located in a dielectric layer (46; Fig. 14A, [0081]) when viewed from a cross section. (Fig. 14A)
Allowable Subject Matter
Claims 16-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or suggest, singularly or in combination, at least the limitations of "a shielding structure, which includes a horizontal part and a vertical part, and the vertical part is located between the high-voltage device region and the MRAM region" as recited in claim 16.
Conclusion
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/HSIN YI HSIEH/Primary Examiner, Art Unit 2899 9/9/2026
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